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DAC8552

FEATURES DESCRIPTION

APPLICATIONS

DACA

DACB

REF

V A

OUT

V B

OUT

Power-Down

ControlLogic

Resistor

Network

Channel

Select

Load

Control

ControlLogic

GND

SYNC

SCLK

24-Bit,

Serial-to-

Parallel

Shift

Data

BufferA

Data

BufferB

DAC

ARegister

DAC

DAC8552

SLAS430A – JULY 2006 – REVISED OCTOBER 2006

16-BIT, DUAL CHANNEL, ULTRA-LOW GLITCH, VOLTAGE OUTPUT

DIGITAL-TO-ANALOG CONVERTER

• Relative Accuracy: 4LSB

The DAC8552 is a 16-bit, dual channel, voltage

output digital-to-analog converter (DAC) offering low

• Glitch Energy: 0.15nV-s

power operation and a flexible serial host interface.

• MicroPower Operation:

Each on-chip precision output amplifier allows

155 µ A per Channel at 2.7V

rail-to-rail output swing to be achieved over the

• Power-On Reset to Zero-Scale

supply range of 2.7V to 5.5V. The device supports a

standard 3-wire serial interface capable of operating

• Power Supply: 2.7V to 5.5V

with input data clock frequencies up to 30MHz for

• 16-Bit Monotonic Over Temperature

= 5V.

• Settling Time: 10 µ s to ± 0.003% FSR

The DAC8552 requires an external reference voltage

• Ultra-Low AC Crosstalk: –100dB Typ

to set the output range of each DAC channel. Also

• Low-Power Serial Interface with

incorporated into the device is a power-on reset

Schmitt-Triggered Inputs

circuit which ensures that the DAC outputs power up

at zero-scale and remain there until a valid write

• On-Chip Output Buffer Amplifier with

takes place. The DAC8552 provides a flexible

Rail-to-Rail Operation

power-down feature, accessed over the serial

• Double-Buffered Input Architecture

interface, that reduces the current consumption of

• Simultaneous or Sequential Output Update

the device to 700nA at 5V.

and Power-down

The low-power consumption of this device in normal

• Available in a Tiny MSOP-8 Package

operation makes it ideally suited for portable,

battery-operated equipment and other low-power

applications. The power consumption is 0.5mW per

channel at 2.7V, reducing to 1 µ W in power-down

• Portable Instrumentation

mode.

• Closed-Loop Servo Control

The DAC8552 is available in a MSOP-8 package

• Process Control

with a specified operating temperature range of

• Data Acquisition Systems

–40 ° C to +105 ° C.

• Programmable Attenuation

• PC Peripherals

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SPI, QSP are trademarks of Motorola, Inc.

Microwire is a trademark of National Semiconductor.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (25 pages)

PAGE 1
DAC8552 DA C8 552 SLAS430A – JULY 2006 – REVISED OCTOBER 2006 16-BIT, DUAL CHANNEL, ULTRA-LOW GLITCH, VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER FEATURES • • • • • • • • • • • • • DESCRIPTION Relative Accuracy: 4LSB Glitch Energy: 0.15nV-s MicroPower Operation: 155µA per Channel at 2.7V Power-On Reset to Zero-Scale Power Supply: 2.7V to 5.5V 16-Bit Monotonic Over Temperature Settling Time: 10µs to ±0.
PAGE 2
DAC8552 www.ti.com SLAS430A – JULY 2006 – REVISED OCTOBER 2006 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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DAC8552 www.ti.com SLAS430A – JULY 2006 – REVISED OCTOBER 2006 ELECTRICAL CHARACTERISTICS (continued) VDD = 2.7V to 5.5V, all specifications –40°C to +105°C (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VREF V OUTPUT CHARACTERISTICS (2) Output voltage range Output voltage settling time 0 To ±0.003% FSR 0200h to FD00h, RL = 2kΩ; 0pF < CL < 200pF 8 RL = 2kΩ; CL = 500pF µs 12 Slew rate Capacitive load stability 10 1.
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DAC8552 www.ti.com SLAS430A – JULY 2006 – REVISED OCTOBER 2006 PIN CONFIGURATION DGK PACKAGE MSOP-8 (Top View) VDD 1 VREF 2 8 GND 7 DIN DAC8552 VOUTB 3 6 SCLK VOUTA 4 5 SYNC PIN DESCRIPTIONS PIN 4 NAME FUNCTION 1 VDD Power supply input, 2.7V to 5.5V 2 VREF Reference voltage input 3 VOUTB Analog output voltage from DAC B 4 VOUTA Analog output voltage from DAC A 5 SYNC Level triggered SYNC input (active LOW). This is the frame synchronization signal for the input data.
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DAC8552 www.ti.com SLAS430A – JULY 2006 – REVISED OCTOBER 2006 SERIAL WRITE OPERATION t9 t1 SCLK 1 24 t8 t3 t4 t2 t7 SYNC t6 t5 DIN DB23 DB0 DB23 TIMING CHARACTERISTICS (1) (2) VDD = 2.7V to 5.5V, all specifications –40°C to +105°C (unless otherwise noted).
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DAC8552 www.ti.com SLAS430A – JULY 2006 – REVISED OCTOBER 2006 TYPICAL CHARACTERISTICS: VDD = 5V At TA = +25°C, unless otherwise noted. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE 1.0 1.0 0.5 0.5 0 -0.5 -1.0 VDD = 5V, VREF = 4.9V, TA = +25°C Channel B Output 0 -0.5 -1.0 0 7.5 8192 16384 24576 32768 40960 49152 Digital Input Code 57344 65536 0 8192 16384 24576 32768 40960 49152 Digital Input Code Figure 1. Figure 2.
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DAC8552 www.ti.com SLAS430A – JULY 2006 – REVISED OCTOBER 2006 TYPICAL CHARACTERISTICS: VDD = 5V (continued) At TA = +25°C, unless otherwise noted. SUPPLY CURRENT vs DIGITAL INPUT CODE SUPPLY CURRENT vs SUPPLY VOLTAGE 600 600 Reference Current Included 500 VDD = VREF = 5.5V 500 400 VDD = VREF = 3.6V 300 450 IDD (mA) IDD (mA) VREF = VDD, All DACs Powered Reference Current Included, No Load 550 400 350 200 300 100 250 0 200 0 2.7 8192 16384 24576 32768 40960 49152 57344 65536 3.1 3.
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DAC8552 www.ti.com SLAS430A – JULY 2006 – REVISED OCTOBER 2006 TYPICAL CHARACTERISTICS: VDD = 5V (continued) At TA = +25°C, unless otherwise noted. SIGNAL-TO-NOISE RATIO vs OUTPUT FREQUENCY 98 VREF = VDD = 5V -1dB FSR Digital Input fS = 1MSPS Measurement Bandwidth = 20kHz 94 VDD = 5V VREF = 4.99V Code = 7FFFh No Load 300 Voltage Noise (nV/ÖHz) 96 SNR (dB) OUTPUT NOISE DENSITY 350 92 90 88 250 200 150 86 100 84 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.
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DAC8552 www.ti.com SLAS430A – JULY 2006 – REVISED OCTOBER 2006 TYPICAL CHARACTERISTICS: VDD = 5V (continued) At TA = +25°C, unless otherwise noted. VDD = 5V VREF = 4.096V From Code: 7FFF To Code: 8000 Glitch: 0.08nV-s VDD = 5V VREF = 4.096V From Code: 8000 To Code: 7FFF Glitch: 0.16nV-s Measured Worst Case Time (400ns/div) Time (400ns/div) Figure 19. Figure 20. GLITCH ENERGY: 5V, 16LSB STEP, RISING EDGE GLITCH ENERGY: 5V, 16LSB STEP, FALLING EDGE VDD = 5V VREF = 4.
PAGE 10
DAC8552 www.ti.com SLAS430A – JULY 2006 – REVISED OCTOBER 2006 TYPICAL CHARACTERISTICS: VDD = 2.7V At TA = +25°C, unless otherwise noted. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE 8 6 4 2 0 -2 -4 -6 -8 LE (LSB) VDD = 2.7V, VREF = 2.5V, TA = +25°C Channel A Output 1.0 1.0 0.5 0.5 DLE (LSB) DLE (LSB) LE (LSB) 8 6 4 2 0 -2 -4 -6 -8 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE 0 -0.5 -1.0 VDD = 2.7V, VREF = 2.5V, TA = +25°C Channel B Output 0 -0.5 -1.
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DAC8552 www.ti.com SLAS430A – JULY 2006 – REVISED OCTOBER 2006 TYPICAL CHARACTERISTICS: VDD = 2.7V (continued) At TA = +25°C, unless otherwise noted. FULL-SCALE SETTLING TIME: 2.7V RISING EDGE FULL-SCALE SETTLING TIME: 2.7V FALLING EDGE Trigger Pulse 2.7V/div Trigger Pulse 2.7V/div VDD = 2.7V VREF = 2.5V From Code: FFFF To Code: 0000 Rising Edge 0.5V/div VDD = 2.7V VREF = 2.5V From Code: 0000 To Code: FFFF Falling Edge 0.
PAGE 12
DAC8552 www.ti.com SLAS430A – JULY 2006 – REVISED OCTOBER 2006 TYPICAL CHARACTERISTICS: VDD = 2.7V (continued) At TA = +25°C, unless otherwise noted. 12 VDD = 2.7V VREF = 2.5V From Code: 8010 To Code: 8000 Glitch: 0.12nV-s VOUT (200mV/div) VDD = 2.7V VREF = 2.5V From Code: 8000 To Code: 8010 Glitch: 0.04nV-s GLITCH ENERGY: 2.7V, 16LSB STEP, FALLING EDGE Time (400ns/div) Time (400ns/div) Figure 37. Figure 38. GLITCH ENERGY: 2.7V, 256LSB STEP, RISING EDGE GLITCH ENERGY: 2.
PAGE 13
DAC8552 www.ti.com SLAS430A – JULY 2006 – REVISED OCTOBER 2006 THEORY OF OPERATION DAC SECTION VREF The architecture of each channel of the DAC8552 consists of a resistor-string DAC followed by an output buffer amplifier. Figure 41 shows a simplified block diagram of the DAC architecture. VREF 50kW RDIVIDER VREF 2 50kW R 62kW DAC Register VOUT REF(+) Resistor String REF(-) R To Output Amplifier (2x Gain) GND Figure 41.
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DAC8552 www.ti.com SLAS430A – JULY 2006 – REVISED OCTOBER 2006 cycle. To assure the lowest power consumption of the device, care should be taken that the levels are as close to each rail as possible. (See the Typical Characteristics section for the Supply Current vs Logic Input Voltage transfer characteristic curve). the destination of the data (or power-down command) between DAC A and DAC B.
PAGE 15
DAC8552 www.ti.com SLAS430A – JULY 2006 – REVISED OCTOBER 2006 SYNC INTERRUPT In a normal write sequence, the SYNC line is kept LOW for at least 24 falling edges of SCLK and the addressed DAC register is updated on the 24th falling edge. However, if SYNC is brought HIGH before the 24th falling edge, it acts as an interrupt to the write sequence; the shift register is reset and the write sequence is discarded.
PAGE 16
DAC8552 www.ti.
PAGE 17
DAC8552 www.ti.com SLAS430A – JULY 2006 – REVISED OCTOBER 2006 MICROPROCESSOR INTERFACING DAC8552 to 8051 INTERFACE DAC8552 to 68HC11 INTERFACE Figure 46 shows a serial interface between the DAC8552 and a typical 8051-type microcontroller. The setup for the interface is as follows: TXD of the 8051 drives SCLK of the DAC8552, while RXD drives the serial data line of the device. The SYNC signal is derived from a bit-programmable pin on the port of the 8051. In this case, port line P3.3 is used.
PAGE 18
DAC8552 www.ti.com SLAS430A – JULY 2006 – REVISED OCTOBER 2006 APPLICATION INFORMATION CURRENT CONSUMPTION The DAC8552 typically consumes 170µA at VDD = 5 V and 155µA at VDD = 2.7V for each active channel, excluding reference current consumption. Additional current consumption can occur at the digital inputs if VIH << VDD. For most efficient power operation, CMOS logic levels are recommended at the digital input to the DAC. In power-down mode, typical current consumption is 700nA.
PAGE 19
DAC8552 www.ti.com SLAS430A – JULY 2006 – REVISED OCTOBER 2006 USING REF02 AS A POWER SUPPLY FOR DAC8552 the DAC8552 is 340µA typical and 500µA max for VDD = 5V. When a DAC output is loaded, the REF02 also needs to supply the current to the load. The typical current required (with a 5kΩ load on a given DAC output) is: 340µA + (5V/5kΩ) = 1.
PAGE 20
DAC8552 www.ti.com SLAS430A – JULY 2006 – REVISED OCTOBER 2006 LAYOUT A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. The DAC8552 offers single-supply operation, and it will often be used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 22
PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DAC8552IDGKR MSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 DAC8552IDGKT MSOP DGK 8 250 330.0 12.4 5.3 3.4 1.4 8.0 12.
PAGE 23
PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC8552IDGKR MSOP DGK 8 2500 346.0 346.0 29.0 DAC8552IDGKT MSOP DGK 8 250 346.0 346.0 29.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.