Datasheet

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DAC8554

FEATURES DESCRIPTION

APPLICATIONS

Data

BufferA

Buffer

Control

Power-Down

ControlLogic

Resistor

Network

ENABLE

SYNC

LDAC

DAC

DACA

Data

BufferD

DAC

DACD

Control

24-Bit

Serial-to-Parallel

ShiftRegister

SCLK

V L

REF

V H

REF

IOV

V A

OUT

V B

OUT

V C

OUT

V D

OUT

A1A0

DAC8554

SLAS431B – JUNE 2005 – REVISED OCTOBER 2006

16-BIT, QUAD-CHANNEL, ULTRA-LOW GLITCH, VOLTAGE OUTPUT

DIGITAL-TO-ANALOG CONVERTER

• Relative Accuracy: 4LSB

The DAC8554 is a 16-bit, quad-channel, voltage

output, digital-to-analog converter (DAC), offering

• Glitch Energy: 0.15nV-s

low-power operation and a flexible serial host

• MicroPower Operation:

interface. It offers monotonicity, good linearity, and

150 µ A per channel at 2.7V

exceptionally low glitch. Each on-chip precision

• Power-On Reset to Zero-Scale

output amplifier allows rail-to-rail output swing to be

achieved over the supply range of 2.7V to 5.5V. The

• Power Supply: +2.7V to +5.5V

device supports a standard 3-wire serial interface

• 16-Bit Monotonic Over Temperature

capable of operating with input data clock

• Settling Time: 10 µ s to ± 0.003% FSR

frequencies up to 50MHz for IOV

= 5V.

• Ultra-Low AC Crosstalk: –100dB Typ

The DAC8554 requires an external reference voltage

• Low Power SPI™ Compatible Serial Interface

to set the output range of each DAC channel. Also

with Schmitt-Triggered Inputs: Up to 50MHz

incorporated into the device is a power-on reset

circuit which ensures that the DAC outputs power up

• On-Chip Output Buffer Amplifier with

at zero-scale and remain there until a valid write

Rail-to-Rail Operation

takes place. The DAC8554 provides a per channel

• Double Buffered Input Architecture

power-down feature, accessed over the serial

• Simultaneous or Sequential Output Update

interface, that reduces the current consumption to

and Power-Down

175nA per channel at 5V.

• 16-Channel Broadcast Capability

The low-power consumption of this device in normal

operation makes it ideally suited to portable

• 1.8V to 5.5V Logic Compatibility

battery-operated equipment and other low-power

• Available in a TSSOP-16 Package

applications. The power consumption is 4.25mW at

5V, reducing to 4 µ W in power-down mode.

The DAC8554 is available in a TSSOP-16 package

• Portable Instrumentation

with a specified operating temperature range of

• Closed-Loop Servo-Control

–40 ° C to +105 ° C.

• Process Control

FUNCTIONAL BLOCK DIAGRAM

• Data Acquisition Systems

• Programmable Attenuation

• PC Peripherals

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SPI, QSPI are trademarks of Motorola, Inc.

Microwire is a trademark of National Semiconductor.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (31 pages)

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DA C8 554 DAC8554 SLAS431B – JUNE 2005 – REVISED OCTOBER 2006 16-BIT, QUAD-CHANNEL, ULTRA-LOW GLITCH, VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER FEATURES • • • • • • • • • • • • • • • Relative Accuracy: 4LSB Glitch Energy: 0.15nV-s MicroPower Operation: 150µA per channel at 2.7V Power-On Reset to Zero-Scale Power Supply: +2.7V to +5.5V 16-Bit Monotonic Over Temperature Settling Time: 10µs to ±0.
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DAC8554 www.ti.com SLAS431B – JUNE 2005 – REVISED OCTOBER 2006 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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DAC8554 www.ti.com SLAS431B – JUNE 2005 – REVISED OCTOBER 2006 ELECTRICAL CHARACTERISTICS (continued) VDD = 2.7V to 5.5V,– 40°C to +105°C range (unless otherwise noted). PARAMETER TEST CONDITIONS MIN Slew rate Capacitive load stability Code change glitch impulse TYP MAX UNIT 1.8 V/µs 470 pF RL = 2kΩ 1000 pF 1LSB change around major carry 0.15 RL = ∞ Digital feedthrough nV-s 0.15 DC crosstalk Full-scale swing on adjacent channel. AVDD = 5V, VREF = 4.096V 0.
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DAC8554 www.ti.com SLAS431B – JUNE 2005 – REVISED OCTOBER 2006 PIN CONFIGURATION VOUTA 1 16 LDAC VOUTB 2 15 ENABLE VREFH 3 14 A1 AVDD 4 13 A0 DAC8554 VREFL 5 12 IOVDD GND 6 11 DIN VOUTC 7 10 SCLK VOUTD 8 9 SYNC PIN DESCRIPTIONS 4 PIN NAME DESCRIPTION 1 VOUTA Analog output voltage from DAC A. 2 VOUTB Analog output voltage from DAC B. 3 VrefH Positive reference voltage input. 4 AVDD Power supply input, 2.7V to 5.5V. 5 VrefL Negative reference voltage input.
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DAC8554 www.ti.com SLAS431B – JUNE 2005 – REVISED OCTOBER 2006 SERIAL WRITE OPERATION t9 t1 SCLK 1 24 t8 t2 t3 t4 t7 SYNC t6 t5 DIN DB23 DB0 DB23 TIMING REQUIREMENTS (1) (2) AVDD = 2.7V to 5.
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DAC8554 www.ti.com SLAS431B – JUNE 2005 – REVISED OCTOBER 2006 TYPICAL CHARACTERISTICS: VDD = 5V At TA = +25°C, unless otherwise noted. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE LE (LSB) 1.0 1.0 0.5 0.5 0 -0.5 -1.0 8 6 4 2 0 -2 -4 -6 -8 0 -0.
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DAC8554 www.ti.com SLAS431B – JUNE 2005 – REVISED OCTOBER 2006 TYPICAL CHARACTERISTICS: VDD = 5V (continued) At TA = +25°C, unless otherwise noted. SUPPLY CURRENT vs LOGIC INPUT VOLTAGE SOURCE CURRENT CAPABILITY (ALL CHANNELS) 6.0 2000 5.6 1600 TA = +25°C, SYNC Input (All other inputs = GND) CH A Powered Up (All other channels in powerdown) Reference Current Included 5.2 IDD (mA) VOUT (V) IOVDD = AVDD = VREF = 5V 4.8 4.4 AVDD = 5.5V VREF = AVDD - 10mV DAC Loaded with FFFFh 1200 800 400 4.
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DAC8554 www.ti.com SLAS431B – JUNE 2005 – REVISED OCTOBER 2006 TYPICAL CHARACTERISTICS: VDD = 5V (continued) At TA = +25°C, unless otherwise noted. HALF-SCALE SETTLING TIME: 5V RISING EDGE HALF-SCALE SETTLING TIME: 5V FALLING EDGE Trigger Pulse: 5V/div Rising Edge 1V/div Trigger Pulse: 5V/div AVDD = 5V, VREF = 4.096V, From Code: CFFF To Code: 4000 AVDD = 5V, VREF = 4.096V, From Code: 4000 To Code: CFFF Falling Edge 1V/div Zoomed Rising Edge 1mV/div 8 Time (2ms/div) Figure 14.
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DAC8554 www.ti.com SLAS431B – JUNE 2005 – REVISED OCTOBER 2006 TYPICAL CHARACTERISTICS: VDD = 5V (continued) At TA = +25°C, unless otherwise noted. GLITCH ENERGY: 5V, 256LSB STEP, FALLING EDGE AVDD = 5V, VREF = 4.096V, From Code: 8000 To Code: 80FF Glitch: Not Detected Theoretical Worst Case Time (400ns/div) Time (400ns/div) Figure 19. Figure 20. OUTPUT NOISE DENSITY SIGNAL-TO-NOISE RATIO vs OUTPUT FREQUENCY 350 98 AVDD = 5V VREF = 4.
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DAC8554 www.ti.com SLAS431B – JUNE 2005 – REVISED OCTOBER 2006 TYPICAL CHARACTERISTICS: VDD = 2.7V At TA = +25°C, unless otherwise noted. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 8 6 4 2 0 -2 -4 -6 -8 VDD = 2.7V, VREF = 2.69V Channel A LE (LSB) LE (LSB) 8 6 4 2 0 -2 -4 -6 -8 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1.0 DLE (LSB) DLE (LSB) 1.0 0.5 0 -0.5 -1.
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DAC8554 www.ti.com SLAS431B – JUNE 2005 – REVISED OCTOBER 2006 TYPICAL CHARACTERISTICS: VDD = 2.7V (continued) At TA = +25°C, unless otherwise noted. SUPPLY CURRENT vs LOGIC INPUT VOLTAGE SOURCE CURRENT CAPABILITY (ALL CHANNELS) 3.0 800 TA = +25°C, SYNC Input (All other inputs = GND) CH A Powered Up (All other channels in powerdown) Reference Current Included 2.7 600 IDD (mA) VOUT (V) IOVDD = AVDD = VREF = 2.7V 2.4 2.1 1.8 400 200 AVDD = 2.7V VREF = AVDD - 10mV DAC Loaded with FFFFh 1.
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DAC8554 www.ti.com SLAS431B – JUNE 2005 – REVISED OCTOBER 2006 TYPICAL CHARACTERISTICS: VDD = 2.7V (continued) At TA = +25°C, unless otherwise noted. VOUT (200mV/div) AVDD = 2.7V, VREF = 2.5V, From Code: 7FFF To Code: 8000 Glitch: 0.08nV-s AVDD = 2.7V, VREF = 2.5V, From Code: 8000 To Code: 7FFF Glitch: 0.16nV-s Measured Worst Case Time (400ns/div) Time (400ns/div) Figure 35. Figure 36. GLITCH ENERGY: 2.7V, 16LSB STEP, RISING EDGE GLITCH ENERGY: 2.7V, 16LSB STEP, FALLING EDGE AVDD = 2.
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DAC8554 www.ti.com SLAS431B – JUNE 2005 – REVISED OCTOBER 2006 TYPICAL CHARACTERISTICS: VDD = 5V and 2.7V At TA = +25°C, unless otherwise noted. SUPPLY CURRENT vs DIGITAL INPUT CODE SINK CURRENT CAPABILITY (ALL CHANNELS) 0.150 1200 VREF = AVDD - 10mV DAC Loaded with 0000h Reference Current Included 1000 0.125 800 IDD (mA) VOUT (V) AVDD = VREF = 5V VDD = 2.7V 0.100 VDD = 5.5V 0.075 600 AVDD = VREF = 2.7V 0.050 400 0.
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DAC8554 www.ti.com SLAS431B – JUNE 2005 – REVISED OCTOBER 2006 THEORY OF OPERATION DAC SECTION VREFH The architecture of each channel of the DAC8554 consists of a resistor-string DAC followed by an output buffer amplifier. Figure 45 shows a simplified block diagram of the DAC architecture. VREFH 50kW RDIVIDER VREF 2 50kW R 62kW VOUT REF(+) Resistor String REF(-) DAC Register R To Output Amplifier (2x Gain) VREFL Figure 45.
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DAC8554 www.ti.com SLAS431B – JUNE 2005 – REVISED OCTOBER 2006 After the 24th falling edge of SCLK is received, the SYNC line may be kept LOW or brought HIGH. In either case, the minimum delay time from the 24th falling SCLK edge to the next falling SYNC edge must be met in order to properly begin the next cycle. To assure the lowest power consumption of the device, care should be taken that the levels are as close to each rail as possible.
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DAC8554 www.ti.com SLAS431B – JUNE 2005 – REVISED OCTOBER 2006 The DAC8554 also supports a number of different load commands. The load commands include broadcast commands to address all the DAC8554s on an SPI bus. The load commands can be summarized as follows: Power-down/data selection is as follows: DB16 is a power-down flag. If this flag is set, then DB15 and DB14 select one of the four power-down modes of the device as described in Table 1.
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DAC8554 www.ti.com SLAS431B – JUNE 2005 – REVISED OCTOBER 2006 SYNC INTERRUPT POWER-ON RESET In a normal write sequence, the SYNC line is kept LOW for at least 24 falling edges of SCLK and the addressed DAC register is updated on the 24th falling edge. However, if SYNC is brought HIGH before the 24th falling edge, it acts as an interrupt to the write sequence; the shift register is reset and the write sequence is discarded.
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DAC8554 www.ti.com SLAS431B – JUNE 2005 – REVISED OCTOBER 2006 POWER-DOWN MODES The DAC8554 utilizes four modes of operation. These modes are accessed by setting three bits (PD2, PD1, and PD0) in the shift register and performing a Load action to the DACs. The DAC8554 offers a very flexible power-down interface based on channel register operation. A channel consists of a single 16-bit DAC with power-down circuitry, a temporary storage register (TR), and a DAC register (DR). TR and DR are both 18 bits wide.
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DAC8554 www.ti.
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DAC8554 www.ti.com SLAS431B – JUNE 2005 – REVISED OCTOBER 2006 Example 3: Power-Down DAC A and DAC B to 1kΩ and Power-Down DAC C and DAC D to 100kΩ Simultaneously • Write power-down command to data buffer A: DAC A to 1kΩ. • • • A1 A0 LD1 LD0 DC DAC Sel 1 DAC Sel 0 PD0 DB15 DB14 DB13 — 0 0 0 0 X 0 0 1 0 1 X — Write power-down command to data buffer B: DAC B to 1kΩ.
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DAC8554 www.ti.com SLAS431B – JUNE 2005 – REVISED OCTOBER 2006 LDAC FUNCTIONALITY The DAC8554 offers both a software and hardware simultaneous update function. The DAC8554 double-buffered architecture has been designed so that new data can be entered for each DAC without disturbing the analog outputs. The software simultaneous update capability is controlled by the load 1 (LD1) and load 0 (LD0) control bits.
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DAC8554 www.ti.com SLAS431B – JUNE 2005 – REVISED OCTOBER 2006 DAC8554 to 68HC11 Interface MICROPROCESSOR INTERFACING DAC8554 to 8051 Interface See Figure 50 for a serial interface between the DAC8554 and a typical 8051-type microcontroller. The setup for the interface is as follows: TXD of the 8051 drives SCLK of the DAC8554, while RXD drives the serial data line of the device. The SYNC signal is derived from a bit-programmable pin on the port of the 8051. In this case, port line P3.3 is used.
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DAC8554 www.ti.com SLAS431B – JUNE 2005 – REVISED OCTOBER 2006 APPLICATION INFORMATION CURRENT CONSUMPTION The DAC8554 typically consumes a maximum of 208µA at AVDD = 5V and 180µA at AVDD = 3V for each active channel, including reference current consumption. Additional current consumption can occur at the digital inputs if VIH << IOVDD. For most efficient power operation, CMOS logic levels are recommended at the digital inputs to the DAC.
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DAC8554 www.ti.com SLAS431B – JUNE 2005 – REVISED OCTOBER 2006 USING THE REF02 AS A POWER SUPPLY FOR THE DAC8554 Due to the extremely low supply current required by the DAC8554, a possible configuration is to use a REF02 (+5V precision voltage reference) to supply the required voltage to the DAC8554 supply input as well as the reference input, as illustrated in Figure 54. This is especially useful if the power supply is quite noisy or if the system supply voltages are at some value other than 5V.
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DAC8554 www.ti.com SLAS431B – JUNE 2005 – REVISED OCTOBER 2006 LAYOUT A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. The DAC8554 offers single-supply operation, and it will often be used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device DAC8554IPWR Package Package Pins Type Drawing TSSOP PW 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 12.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) 5.6 1.6 8.0 W Pin1 (mm) Quadrant 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC8554IPWR TSSOP PW 16 2000 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.