Datasheet

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DAC8565

24-BitShiftRegister

SYNC

SCLK

DataBufferA

DACRegisterA

DataBufferB

DACRegisterB

DataBufferC

DACRegisterC

DataBufferD

DACRegisterD

Buffer

Control

ControlLogic

2.5V

Reference

Power-Down

ControlLogic

16-BitDAC

V A

OUT

V B

OUT

V C

OUT

V D

OUT

GND

LDAC ENABLE

RSTSEL

RST

DAC8565

REF REF

H/V OUT

IOV

REF

DAC8565

www.ti.com

SBAS411C –JUNE 2007–REVISED MARCH 2011

16-Bit, Quad Channel, Ultra-Low Glitch, Voltage Output

Digital-to-Analog Converter with 2.5V, 2ppm/°C Internal Reference

Check for Samples: DAC8565

FEATURES

DESCRIPTION

The DAC8565 is a low-power, voltage-output,

234

• Relative Accuracy: 4LSB

four-channel, 16-bit digital-to-analog converter (DAC).

• Glitch Energy: 0.15nV-s

The device includes a 2.5V, 2ppm/°C internal

• Internal Reference:

reference (enabled by default), giving a full-scale

output voltage range of 2.5V. The internal reference

– 2.5V Reference Voltage (enabled by default)

has an initial accuracy of 0.004% and can source up

– 0.004% Initial Accuracy (typ)

to 20mA at the V

REF

H/V

REF

OUT pin. The device is

– 2ppm/°C Temperature Drift (typ)

monotonic, provides very good linearity, and

minimizes undesired code-to-code transient voltages

– 5ppm/°C Temperature Drift (max)

(glitch). The DAC8565 use a versatile 3-wire serial

– 20mA Sink/Source Capability

interface that operates at clock rates up to 50MHz. It

• Power-On Reset to Zero-Scale or Midscale

is compatible with standard SPI™, QSPI™,

Microwire™, and digital signal processor (DSP)

• Asynchronous Clear to Zero-Scale or Midscale

interfaces.

• Ultra-Low Power Operation: 1mA at 5V

The DAC8565 incorporates a power-on-reset circuit

• Wide Power Supply Range: +2.7V to +5.5V

that ensures the DAC output powers up at either

• 16-Bit Monotonic Over Temperature Range

zero-scale or midscale until a valid code is written to

• Settling Time: 10μs to ±0.003% Full-Scale

the device. The device contains a power-down

Range (FSR)

feature, accessed over the serial interface, that

reduces the current consumption of the device to

• Low-Power Serial Interface with

1.3μA at 5V. The low power consumption, internal

Schmitt-Triggered Inputs: Up to 50MHz

reference, and small footprint make this device ideal

• On-Chip Output Buffer Amplifier with

for portable, battery-operated equipment. The power

Rail-to-Rail Operation

consumption is 2.9mW at 3V, reducing to 1.5μW in

• 1.8V to 5.5V Logic Compatibility

power-down mode.

• Temperature Range: –40°C to +105°C

The DAC8565 is drop-in and functionally compatible

with the DAC7564 and DAC8164, and functionally

APPLICATIONS

compatible with the DAC7565, DAC8165, and

DAC8564. All these devices are available in a

• Portable Instrumentation

TSSOP-16 package.

• Closed-Loop Servo-Control

• Process Control, PLCs

• Data Acquisition Systems

• Programmable Attenuation

• PC Peripherals

DEVICES 16-BIT 14-BIT 12-BIT

Pin and

Functionally DAC8565 DAC8165 DAC7565

Compatible

Functionally

DAC8564 DAC8164 DAC7564

Compatible

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2SPI, QSPI are trademarks of Motorola, Inc.

3Microwire is a trademark of National Semiconductor.

4All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (49 pages)

PAGE 1
DA DAC8565 C8 565 SBAS411C – JUNE 2007 – REVISED MARCH 2011 www.ti.com 16-Bit, Quad Channel, Ultra-Low Glitch, Voltage Output Digital-to-Analog Converter with 2.5V, 2ppm/°C Internal Reference Check for Samples: DAC8565 FEATURES DESCRIPTION • Relative Accuracy: 4LSB • Glitch Energy: 0.15nV-s • Internal Reference: – 2.5V Reference Voltage (enabled by default) – 0.
PAGE 2
DAC8565 SBAS411C – JUNE 2007 – REVISED MARCH 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
PAGE 3
DAC8565 SBAS411C – JUNE 2007 – REVISED MARCH 2011 www.ti.com ELECTRICAL CHARACTERISTICS At AVDD = 2.7V to 5.5V, –40°C to +105°C range, and data format is straight binary (unless otherwise noted). DAC8565 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ±4 ±12 LSB STATIC PERFORMANCE (1) Resolution 16 Relative accuracy Measured by the line passing through codes 485 and 64714 Differential nonlinearity 16-bit monotonic DAC8565A, DAC8565C Bits ±4 ±8 LSB ±0.
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DAC8565 SBAS411C – JUNE 2007 – REVISED MARCH 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) At AVDD = 2.7V to 5.5V, –40°C to +105°C range, and data format is straight binary (unless otherwise noted). DAC8565 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT REFERENCE OUTPUT Output voltage TA = +25°C 2.4975 2.5 2.5025 V Initial accuracy TA = +25°C –0.1 ±0.004 0.
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DAC8565 SBAS411C – JUNE 2007 – REVISED MARCH 2011 www.ti.com PIN CONFIGURATIONS PW PACKAGE TSSOP-16 (Top View) VOUTA 1 16 LDAC VOUTB 2 15 ENABLE VREFH/VREFOUT 3 14 RSTSEL AVDD 4 13 RST DAC8565 VREFL 5 12 IOVDD GND 6 11 DIN VOUTC 7 10 SCLK VOUTD 8 9 SYNC PIN DESCRIPTIONS PIN NAME 1 VOUTA Analog output voltage from DAC A DESCRIPTION 2 VOUTB Analog output voltage from DAC B 3 VREFH/ VREFOUT Positive reference input / reference output 2.5V if internal reference used.
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DAC8565 SBAS411C – JUNE 2007 – REVISED MARCH 2011 www.ti.
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DAC8565 SBAS411C – JUNE 2007 – REVISED MARCH 2011 www.ti.com TIMING REQUIREMENTS (1) (2) At AVDD = IOVDD= 2.7V to 5.5V and –40°C to +105°C range (unless otherwise noted).
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DAC8565 SBAS411C – JUNE 2007 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: Internal Reference At TA = +25°C, unless otherwise noted. INTERNAL REFERENCE VOLTAGE vs TEMPERATURE (Grades A and B) 2.503 2.503 2.502 2.502 2.501 2.501 VREF (V) VREF (V) INTERNAL REFERENCE VOLTAGE vs TEMPERATURE (Grades C and D) 2.500 2.499 2.500 2.499 2.498 2.498 10 Units Shown 2.497 -40 -20 0 20 40 60 80 100 13 Units Shown 2.
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DAC8565 SBAS411C – JUNE 2007 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: Internal Reference (continued) At TA = +25°C, unless otherwise noted. INTERNAL REFERENCE NOISE DENSITY vs FREQUENCY INTERNAL REFERENCE NOISE 0.1Hz TO 10Hz 300 250 VNOISE (5mV/div) VN (nV/ÖHz) 12mV (peak-to-peak) 200 Reference Unbuffered CREF = 0mF 150 100 50 CREF = 4.8mF 0 10 100 1k 10k 100k Time (2s/div) 1M Frequency (Hz) Figure 7. Figure 8.
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DAC8565 SBAS411C – JUNE 2007 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 5V At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted. Channel A AVDD = 5.0V, External VREF = 4.99V LE (LSB) 6 4 2 0 -2 -4 -6 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (–40°C) 1.0 0.5 0.5 0 -0.5 -1.
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DAC8565 SBAS411C – JUNE 2007 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued) At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted. LE (LSB) 6 4 2 0 -2 -4 -6 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (+25°C) Channel C AVDD = 5.0V, External VREF = 4.99V 1.0 0.5 0.5 0 -0.5 -1.0 16384 24576 32768 40960 49152 0 -0.
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DAC8565 SBAS411C – JUNE 2007 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued) At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted. OFFSET ERROR vs TEMPERATURE FULL-SCALE ERROR vs TEMPERATURE 4 0.50 AVDD = 5V Internal VREF Enabled Full-Scale Error (mV) 3 Offset Error (mV) AVDD = 5V Internal VREF Enabled Ch C 2 1 Ch D Ch A 0 Ch B -1 -40 -20 20 0 60 40 80 100 Ch C 0.
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DAC8565 SBAS411C – JUNE 2007 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued) At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted. POWER-SUPPLY CURRENT vs DIGITAL INPUT CODE POWER-SUPPLY CURRENT vs TEMPERATURE 1400 AVDD = 5.5V Internal VREF Included 1200 Power-Supply Current (mA) Power-Supply Current (mA) 1300 1100 1000 900 800 0 AVDD = 5.
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DAC8565 SBAS411C – JUNE 2007 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued) At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted. TOTAL HARMONIC DISTORTION vs OUTPUT FREQUENCY -40 TOTAL HARMONIC DISTORTION vs OUTPUT FREQUENCY -40 AVDD = 5V, External VREF = 4.
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DAC8565 SBAS411C – JUNE 2007 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued) At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted. SIGNAL-TO-NOISE RATIO vs OUTPUT FREQUENCY POWER SPECTRAL DENSITY 0 94 AVDD = 5V, External VREF = 4.
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DAC8565 SBAS411C – JUNE 2007 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued) At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted. AVDD = 5V Int VREF = 2.5V From Code: 7FFFh To Code: 8000h Glitch: 0.08nV-s GLITCH ENERGY: 5V, 1LSB STEP, FALLING EDGE VOUT (500mV/div) VOUT (500mV/div) GLITCH ENERGY: 5V, 1LSB STEP, RISING EDGE AVDD = 5V Int VREF = 2.
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DAC8565 SBAS411C – JUNE 2007 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued) At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted. DAC OUTPUT NOISE DENSITY vs FREQUENCY (1) 1200 DAC OUTPUT NOISE DENSITY vs FREQUENCY (2) 400 Internal Reference Enabled No Load at VREFH/VREFOUT Pin 1000 DAC = Full-Scale Internal Reference Enabled 4.
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DAC8565 SBAS411C – JUNE 2007 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 3.6V At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless otherwise noted POWER-SUPPLY CURRENT vs LOGIC INPUT VOLTAGE POWER-SUPPLY CURRENT vs TEMPERATURE 1400 2400 Power-Supply Current (mA) Power-Supply Current (mA) AVDD = IOVDD = 3.6V, Internal VREF Included SYNC Input (all other digital inputs = GND) 2000 1600 Sweep from 0V to 3.
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DAC8565 SBAS411C – JUNE 2007 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless otherwise noted Channel A AVDD = 2.7V, Internal VREF = 2.5V LE (LSB) 6 4 2 0 -2 -4 -6 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (–40°C) 1.0 0.5 0.5 0 -0.5 -1.0 16384 24576 32768 40960 49152 0 -0.
PAGE 20
DAC8565 SBAS411C – JUNE 2007 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued) At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless otherwise noted LE (LSB) 6 4 2 0 -2 -4 -6 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (+25°C) Channel C AVDD = 2.7V, Internal VREF = 2.5V 1.0 0.5 0.5 0 -0.5 -1.
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DAC8565 SBAS411C – JUNE 2007 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued) At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless otherwise noted OFFSET ERROR vs TEMPERATURE FULL-SCALE ERROR vs TEMPERATURE 4 0.50 AVDD = 2.7V Internal VREF Enabled Full-Scale Error (mV) 3 Offset Error (mV) AVDD = 2.
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DAC8565 SBAS411C – JUNE 2007 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued) At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless otherwise noted POWER-SUPPLY CURRENT vs DIGITAL INPUT CODE POWER-SUPPLY CURRENT vs LOGIC INPUT VOLTAGE 1600 AVDD = 2.7V Internal VREF Included 1200 AVDD = 2.
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DAC8565 SBAS411C – JUNE 2007 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued) At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless otherwise noted AVDD = 2.7V Int VREF = 2.5V From Code: 7FFFh To Code: 8000h Glitch: 0.08nV-s GLITCH ENERGY: 2.7V, 1LSB STEP, FALLING EDGE VOUT (200mV/div) VOUT (200mV/div) GLITCH ENERGY: 2.7V, 1LSB STEP, RISING EDGE AVDD = 2.7V Int VREF = 2.
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DAC8565 SBAS411C – JUNE 2007 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued) At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless otherwise noted POWER-SUPPLY CURRENT vs TEMPERATURE POWER-DOWN CURRENT vs TEMPERATURE 1300 2.0 AVDD = 2.7V Internal VREF Included DAC Loaded with 8000h AVDD = 2.
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DAC8565 SBAS411C – JUNE 2007 – REVISED MARCH 2011 www.ti.com THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER (DAC) The DAC8565 architecture consists of a string DAC followed by an output buffer amplifier. Figure 92 shows a block diagram of the DAC architecture. VREFH 50kW 50kW code loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier by closing one of the switches connecting the string to the amplifier.
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DAC8565 SBAS411C – JUNE 2007 – REVISED MARCH 2011 www.ti.com INTERNAL REFERENCE VREF The DAC8565 includes a 2.5V internal reference that is enabled by default. The internal reference is externally available at the VREFH/VREFOUT pin. A minimum 100nF capacitor is recommended between the reference output and GND for noise filtering. Reference Disable The internal reference of the DAC8565 is a bipolar transistor-based, precision bandgap voltage reference. Figure 94 shows the basic bandgap topology.
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DAC8565 SBAS411C – JUNE 2007 – REVISED MARCH 2011 www.ti.com SERIAL INTERFACE The DAC8565 has a 3-wire serial interface (SYNC, SCLK, and DIN) compatible with SPI, QSPI, and Microwire interface standards, as well as most DSPs. See the Serial Write Operation timing diagram for an example of a typical write sequence. The DAC8565 input shift register is 24 bits wide, consisting of eight control bits (DB23 to DB16) and 16 data bits (DB15 to DB0).
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DAC8565 SBAS411C – JUNE 2007 – REVISED MARCH 2011 www.ti.com LD1 (DB21) and LD0 (DB20) control the updating of each analog output with the specified 16-bit data value or power-down command. Bit DB19 must always be '0'. The DAC channel select bits (DB18, DB17) control the destination of the data (or power-down command) from DAC A to DAC D. The final control bit, PD0 (DB16), selects the power-down mode of the DAC8565 channels as well as the power-down mode of the internal reference.
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DAC8565 SBAS411C – JUNE 2007 – REVISED MARCH 2011 www.ti.com SYNC INTERRUPT LDAC FUNCTIONALITY In a normal write sequence, the SYNC line stays low for at least 24 falling edges of SCLK and the addressed DAC register updates on the 24th falling edge. However, if SYNC is brought high before the 24th falling edge, it acts as an interrupt to the write sequence; the shift register resets and the write sequence is discarded.
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DAC8565 SBAS411C – JUNE 2007 – REVISED MARCH 2011 www.ti.com POWER-DOWN MODES The DAC8565 has two separate sets of power-down commands. One set is for the DAC channels and the other set is for the internal reference. For more information on powering down the reference, see the Enable/Disable Internal Reference section. DAC Power-Down Commands The DAC8565 use four modes of operation. These modes are accessed by setting three bits (PD2, PD1, and PD0) in the shift register.
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DAC8565 SBAS411C – JUNE 2007 – REVISED MARCH 2011 www.ti.com OPERATING EXAMPLES: DAC8565 For the following examples, X = don't care. Value can be either '0' or '1'.
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DAC8565 SBAS411C – JUNE 2007 – REVISED MARCH 2011 www.ti.com Example 3: Power-Down DAC A and DAC B to 1kΩ and Power-Down DAC C and DAC D to 100kΩ Simultaneously • 1st: Write power-down command to data buffer A: DAC A to 1kΩ.
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DAC8565 SBAS411C – JUNE 2007 – REVISED MARCH 2011 www.ti.
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DAC8565 SBAS411C – JUNE 2007 – REVISED MARCH 2011 www.ti.com APPLICATION INFORMATION INTERNAL REFERENCE The internal reference of the DAC8565 does not require an external load capacitor for stability because it is stable with any capacitive load. However, for improved noise performance, an external load capacitor of 150nF or larger connected to the VREFH/VREFOUT output is recommended. Figure 97 shows the typical connections required for operation of the DAC8565 internal reference.
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DAC8565 SBAS411C – JUNE 2007 – REVISED MARCH 2011 www.ti.com Load Regulation Thermal Hysteresis Load regulation is defined as the change in reference output voltage as a result of changes in load current. The load regulation of the internal reference is measured using force and sense contacts as shown in Figure 98. The force and sense lines reduce the impact of contact and trace resistance, resulting in accurate measurement of the load regulation contributed solely by the internal reference.
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DAC8565 SBAS411C – JUNE 2007 – REVISED MARCH 2011 www.ti.com BIPOLAR OPERATION USING THE DAC8565 The DAC8565 is designed for single-supply operation, but a bipolar output range is also possible using the circuit in either Figure 99 or Figure 100. The circuit shown gives an output voltage range of ±VREF. Rail-to-rail operation at the amplifier output is achievable using an OPA703 as the output amplifier.
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DAC8565 SBAS411C – JUNE 2007 – REVISED MARCH 2011 www.ti.com DAC8565 to Microwire Interface MICROPROCESSOR INTERFACING DAC SPI Interfacing Care must be taken with the digital control signals that are applied directly to the DAC, especially with the SYNC pin. The SYNC pin must not be toggled without having a full SCLK pulse in between. If this condition is violated, the SPI interface locks up in an erroneous state, causing the DAC to behave incorrectly and have errors.
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DAC8565 SBAS411C – JUNE 2007 – REVISED MARCH 2011 www.ti.com LAYOUT A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. The DAC8565 offers single-supply operation, and is often used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it is to keep digital noise from appearing at the output.
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DAC8565 SBAS411C – JUNE 2007 – REVISED MARCH 2011 www.ti.com PARAMETER DEFINITIONS With the increased complexity of many different specifications listed in product data sheets, this section summarizes selected specifications related to digital-to-analog converters. STATIC PERFORMANCE Static performance parameters are specifications such as differential nonlinearity (DNL) or integral nonlinearity (INL). These are dc specifications and provide information on the accuracy of the DAC.
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DAC8565 SBAS411C – JUNE 2007 – REVISED MARCH 2011 www.ti.com Power-Supply Rejection Ratio (PSRR) Channel-to-Channel DC Crosstalk Power-supply rejection ratio (PSRR) is defined as the ratio of change in output voltage to a change in supply voltage for a full-scale output of the DAC. The PSRR of a device indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is measured in decibels (dB).
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DAC8565 SBAS411C – JUNE 2007 – REVISED MARCH 2011 www.ti.com DAC Output Noise Density Full-Scale Range (FSR) Output noise density is defined as internally-generated random noise. Random noise is characterized as a spectral density (nV/√Hz). It is measured by loading the DAC to midscale and measuring noise at the output.
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DAC8565 SBAS411C – JUNE 2007 – REVISED MARCH 2011 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (March 2008) to Revision C Page • Changed Output Voltage parameter min/max values from 2.4995 and 2.5005 to 2.4975 and 2.5025, respectively ........... 4 • Changed Initial Accuracy parameter min/max values from –0.02 and 0.02 to –0.1 and 0.1, respectively ...........................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 4-Mar-2011 ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DAC8565IAPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 DAC8565IBPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 DAC8565ICPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC8565IAPWR TSSOP PW 16 2000 367.0 367.0 35.0 DAC8565IBPWR TSSOP PW 16 2000 367.0 367.0 35.0 DAC8565ICPWR TSSOP PW 16 2000 367.0 367.0 35.0 DAC8565IDPWR TSSOP PW 16 2000 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.