Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - DA converter (DAC) TSSOP 16

DAC7568

DAC8168

DAC8568

DataBufferA

DACRegisterA

BufferControl RegisterControl

ControlLogic

32-BitShiftRegister

Power-Down

ControlLogic

REF REF

IN/V OUT

12-/14-/16-Bit

DAC

CLR

LDACGND

SCLK

SYNC

2.5V

Reference

12-/14-/16-Bit

DAC

DataBufferB

DACRegisterB

12-/14-/16-Bit

DAC

DataBufferC

DataBufferD

DataBufferE

DataBufferF

DataBufferG

DACRegisterC

DACRegisterD

DACRegisterE

DACRegisterF

DACRegisterG

12-/14-/16-Bit

DAC

12-/14-/16-Bit

DAC

12-/14-/16-Bit

DAC

12-/14-/16-Bit

DAC

12-/14-/16-Bit

DAC

V H

OUT

DataBufferH

DACRegisterH

V G

OUT

V F

OUT

V E

OUT

V D

OUT

V C

OUT

V B

OUT

V A

OUT

DAC7568

DAC8168

DAC8568

www.ti.com

SBAS430D –JANUARY 2009–REVISED MAY 2012

12-/14-/16-Bit, Octal-Channel, Ultralow Glitch, Voltage Output

DIGITAL-TO-ANALOG CONVERTERS with 2.5V, 2ppm/°C Internal Reference

Check for Samples: DAC7568, DAC8168, DAC8568

FEATURES

APPLICATIONS

234

• Relative Accuracy:

• Portable Instrumentation

– DAC7568 (12-Bit): 0.3 LSB INL • Closed-Loop Servo-Control/Process Control

– DAC8168 (14-Bit): 1 LSB INL • Data Acquisition Systems

– DAC8568 (16-Bit): 4 LSB INL • Programmable Attenuation, Digital Gain, and

Offset Adjustment

• Glitch Energy: 0.1nV-s

• Programmable Voltage and Current Sources

• Internal Reference:

– 2.5V Reference Voltage (disabled by

DESCRIPTION

default)

The DAC7568, DAC8168, and DAC8568 are low-

– 0.004% Initial Accuracy (typ)

power, voltage-output, eight-channel, 12-, 14-, and

– 2ppm/°C Temperature Drift (typ)

16-bit digital-to-analog converters (DACs),

respectively. These devices include a 2.5V, 2ppm/°C

– 5ppm/°C Temperature Drift (max)

internal reference (disabled by default), giving a full-

– 20mA Sink/Source Capability

scale output voltage range of 2.5V or 5V. The internal

• Power-On Reset to Zero Scale or Midscale

reference has an initial accuracy of 0.004% and can

source up to 20mA at the V

REF

IN/V

REF

OUT pin.

• Ultralow Power Operation: 1.25mA at 5V

These devices are monotonic, providing excellent

Including Internal Reference Current

linearity and minimizing undesired code-to-code

• Wide Power-Supply Range: +2.7V to +5.5V

transient voltages (glitch). They use a versatile 3-wire

• Monotonic Over Entire Temperature Range

serial interface that operates at clock rates up to

50MHz. The interface is compatible with standard

• Low-Power Serial Interface with Schmitt-

SPI™, QSPI™, Microwire™, and digital signal

Triggered Inputs: Up to 50MHz

processor (DSP) interfaces.

• On-Chip Output Buffer Amplifier with Rail-to-

The DAC7568, DAC8168, and DAC8568 incorporate

Rail Operation

a power-on-reset circuit that ensures the DAC output

• Temperature Range: –40°C to +125°C

powers up at either zero scale or midscale until a

valid code is written to the device. These devices

contain a power-down feature, accessed over the

serial interface, that reduces current consumption to

typically 0.18μA at 5V. Power consumption (including

internal reference) is typically 2.9mW at 3V, reducing

to less than 1μW in power-down mode. The low

power consumption, internal reference, and small

footprint make these devices ideal for portable,

battery-operated equipment.

The DAC7568, DAC8168, and DAC8568 are drop-in

and function-compatible with each other, and are

available in TSSOP-16 and TSSOP-14 packages.

DEVICE COMPARISON 12-BIT 14-BIT 16-BIT

Pin- and Function-

DAC7568 DAC8168 DAC8568

Compatible

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2SPI, QSPI are trademarks of Motorola, Inc.

3Microwire is a trademark of National Semiconductor.

4All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (65 pages)

PAGE 1
DAC7568 DAC8168 DAC8568 www.ti.com SBAS430D – JANUARY 2009 – REVISED MAY 2012 12-/14-/16-Bit, Octal-Channel, Ultralow Glitch, Voltage Output DIGITAL-TO-ANALOG CONVERTERS with 2.5V, 2ppm/°C Internal Reference Check for Samples: DAC7568, DAC8168, DAC8568 FEATURES APPLICATIONS • Relative Accuracy: – DAC7568 (12-Bit): 0.3 LSB INL – DAC8168 (14-Bit): 1 LSB INL – DAC8568 (16-Bit): 4 LSB INL • Glitch Energy: 0.1nV-s • Internal Reference: – 2.5V Reference Voltage (disabled by default) – 0.
PAGE 2
DAC7568 DAC8168 DAC8568 SBAS430D – JANUARY 2009 – REVISED MAY 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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DAC7568 DAC8168 DAC8568 www.ti.com SBAS430D – JANUARY 2009 – REVISED MAY 2012 ELECTRICAL CHARACTERISTICS At AVDD = 2.7V to 5.5V and over –40°C to +125°C (unless otherwise noted).
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DAC7568 DAC8168 DAC8568 SBAS430D – JANUARY 2009 – REVISED MAY 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) At AVDD = 2.7V to 5.5V and over –40°C to +125°C (unless otherwise noted).
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DAC7568 DAC8168 DAC8568 www.ti.com SBAS430D – JANUARY 2009 – REVISED MAY 2012 ELECTRICAL CHARACTERISTICS (continued) At AVDD = 2.7V to 5.5V and over –40°C to +125°C (unless otherwise noted). DAC7568/DAC8168/DAC8568 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER REQUIREMENTS AVDD 2.
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DAC7568 DAC8168 DAC8568 SBAS430D – JANUARY 2009 – REVISED MAY 2012 www.ti.
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DAC7568 DAC8168 DAC8568 www.ti.com SBAS430D – JANUARY 2009 – REVISED MAY 2012 TIMING DIAGRAM t2 t1 t3 SCLK t4 t6 t5 t8 t7 SYNC t9 DIN t10 DB31 DB0 t11 t12 LDAC(1) t13 t14 LDAC(2) t15 CLR (1) Asynchronous LDAC update mode. For more information and details, see the LDAC Functionality section. (2) Synchronous LDAC update mode. For more information and details, see the LDAC Functionality section. Figure 1. Serial Write Operation TIMING REQUIREMENTS (1) (2) At AVDD = 2.7V to 5.
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DAC7568 DAC8168 DAC8568 SBAS430D – JANUARY 2009 – REVISED MAY 2012 www.ti.com TYPICAL CHARACTERISTICS: Internal Reference At TA = +25°C, unless otherwise noted. INTERNAL REFERENCE VOLTAGE vs TEMPERATURE (Grades A and B) 2.503 2.503 2.502 2.502 2.501 2.501 VREF (V) VREF (V) INTERNAL REFERENCE VOLTAGE vs TEMPERATURE (Grades C and D) 2.500 2.499 2.500 2.499 2.498 2.498 10 Units Shown 2.497 -40 -25 -10 5 20 35 50 65 80 95 110 125 13 Units Shown 2.
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DAC7568 DAC8168 DAC8568 www.ti.com SBAS430D – JANUARY 2009 – REVISED MAY 2012 TYPICAL CHARACTERISTICS: Internal Reference (continued) At TA = +25°C, unless otherwise noted. REFERENCE OUTPUT TEMPERATURE DRIFT (0°C to +125°C, Grades C and D) LONG-TERM STABILITY/DRIFT 200 40 Typ: 1.2ppm/°C Max: 3ppm/°C 150 100 30 50 Drift (ppm) Population (%) (1) 20 0 -50 Average -100 10 -150 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 5.
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DAC7568 DAC8168 DAC8568 SBAS430D – JANUARY 2009 – REVISED MAY 2012 www.ti.com TYPICAL CHARACTERISTICS: Internal Reference (continued) At TA = +25°C, unless otherwise noted. INTERNAL REFERENCE VOLTAGE vs LOAD CURRENT (Grades C and D) INTERNAL REFERENCE VOLTAGE vs LOAD CURRENT (Grades A and B) 2.505 2.505 2.504 2.504 2.503 2.503 2.502 -40°C 2.501 VREF (V) VREF (V) 2.502 2.500 2.499 +25°C 2.498 2.501 +25°C 2.500 2.499 2.498 +125°C 2.497 +125°C 2.497 -40°C 2.496 2.496 2.
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DAC7568 DAC8168 DAC8568 www.ti.com SBAS430D – JANUARY 2009 – REVISED MAY 2012 TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5V Channel-specific information provided as examples. At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted.
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DAC7568 DAC8168 DAC8568 SBAS430D – JANUARY 2009 – REVISED MAY 2012 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5V (continued) Channel-specific information provided as examples. At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted.
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DAC7568 DAC8168 DAC8568 www.ti.com SBAS430D – JANUARY 2009 – REVISED MAY 2012 TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5V (continued) Channel-specific information provided as examples. At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted.
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DAC7568 DAC8168 DAC8568 SBAS430D – JANUARY 2009 – REVISED MAY 2012 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5V (continued) Channel-specific information provided as examples. At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted. OFFSET ERROR vs TEMPERATURE POWER-SUPPLY CURRENT vs TEMPERATURE 1.6 1100 AVDD = 5.5V Internal Reference Disabled Offset Error (mV) 0.8 0.4 0 -0.4 Ch A Ch B Ch C Ch D -0.8 AVDD = 5.
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DAC7568 DAC8168 DAC8568 www.ti.com SBAS430D – JANUARY 2009 – REVISED MAY 2012 TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5V (continued) Channel-specific information provided as examples. At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted. SOURCE CURRENT AT POSITIVE RAIL (Grades C and D) SINK CURRENT AT NEGATIVE RAIL (All Grades) 0.6 5.5 Channel C Channel C 5.0 0.4 VOUT (V) VOUT (V) 4.5 4.0 3.5 0.2 3.0 AVDD = 5.
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DAC7568 DAC8168 DAC8568 SBAS430D – JANUARY 2009 – REVISED MAY 2012 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5V (continued) Channel-specific information provided as examples. At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted. POWER-SUPPLY CURRENT vs DIGITAL INPUT CODE 1.1 1.4 1.0 1.3 Power-Supply Current (mA) Power-Supply Current (mA) POWER-SUPPLY CURRENT vs DIGITAL INPUT CODE 0.9 0.8 0.7 0.6 AVDD = 5.
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DAC7568 DAC8168 DAC8568 www.ti.com SBAS430D – JANUARY 2009 – REVISED MAY 2012 TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5V (continued) Channel-specific information provided as examples. At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted. POWER-SUPPLY CURRENT vs LOGIC INPUT VOLTAGE POWER-SUPPLY CURRENT vs LOGIC INPUT VOLTAGE 3200 AVDD = 5.
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DAC7568 DAC8168 DAC8568 SBAS430D – JANUARY 2009 – REVISED MAY 2012 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5V (continued) Channel-specific information provided as examples. At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted. SECOND HARMONIC DISTORTION vs OUTPUT FREQUENCY POWER SPECTRAL DENSITY 0 -40 AVDD = 5.
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DAC7568 DAC8168 DAC8568 www.ti.com SBAS430D – JANUARY 2009 – REVISED MAY 2012 TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5V (continued) Channel-specific information provided as examples. At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted. HALF-SCALE SETTLING TIME: 5V RISING EDGE HALF-SCALE SETTLING TIME: 5V FALLING EDGE AVDD = 5.5V From Code: 4000h To Code: C000h Internal Reference Enabled AVDD = 5.
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DAC7568 DAC8168 DAC8568 SBAS430D – JANUARY 2009 – REVISED MAY 2012 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5V (continued) Channel-specific information provided as examples. At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted. GLITCH ENERGY: 5V, 1LSB STEP, RISING EDGE GLITCH ENERGY: 5V, 1LSB STEP, FALLING EDGE AVDD = 5.5V From Code:8000h To Code: 7FFFh Channel C as Example Glitch Impulse ~0.
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DAC7568 DAC8168 DAC8568 www.ti.com SBAS430D – JANUARY 2009 – REVISED MAY 2012 TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5V (continued) Channel-specific information provided as examples. At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted. DAC OUTPUT NOISE DENSITY vs FREQUENCY (1) DAC OUTPUT NOISE 0.1Hz TO 10Hz 600 VNOISE (1mV/div) 500 Noise (nV/ÖHz) AVDD = 5.5V DAC = Midscale, No Load Internal Reference = 2.
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DAC7568 DAC8168 DAC8568 SBAS430D – JANUARY 2009 – REVISED MAY 2012 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 3.6V Channel-specific information provided as examples. At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless otherwise noted POWER-SUPPLY CURRENT vs DIGITAL INPUT CODE POWER-SUPPLY CURRENT vs TEMPERATURE 1.30 900 AVDD = 3.6V Internal Reference Disabled Power-Supply Current (mA) Power-Supply Current (mA) 1.25 1.20 1.
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DAC7568 DAC8168 DAC8568 www.ti.com SBAS430D – JANUARY 2009 – REVISED MAY 2012 TYPICAL CHARACTERISTICS: DAC at AVDD = 3.6V (continued) Channel-specific information provided as examples.
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DAC7568 DAC8168 DAC8568 SBAS430D – JANUARY 2009 – REVISED MAY 2012 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V Channel-specific information provided as examples.
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DAC7568 DAC8168 DAC8568 www.ti.com SBAS430D – JANUARY 2009 – REVISED MAY 2012 TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued) Channel-specific information provided as examples.
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DAC7568 DAC8168 DAC8568 SBAS430D – JANUARY 2009 – REVISED MAY 2012 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued) Channel-specific information provided as examples.
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DAC7568 DAC8168 DAC8568 www.ti.com SBAS430D – JANUARY 2009 – REVISED MAY 2012 TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued) Channel-specific information provided as examples. At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless otherwise noted OFFSET ERROR vs TEMPERATURE POWER-SUPPLY CURRENT vs TEMPERATURE 900 1.6 AVDD = 2.7V Internal Reference Disabled Offset Error (mV) 0.8 0.4 0 -0.4 Ch A Ch B Ch C Ch D -0.8 -1.
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DAC7568 DAC8168 DAC8568 SBAS430D – JANUARY 2009 – REVISED MAY 2012 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued) Channel-specific information provided as examples. At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless otherwise noted SOURCE CURRENT AT POSITIVE RAIL (Grades A and B) SINK CURRENT AT NEGATIVE RAIL (All Grades) 2.7 0.6 Channel A Channel A 2.5 VOUT (V) VOUT (V) 0.4 2.3 0.2 2.1 AVDD = 2.
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DAC7568 DAC8168 DAC8568 www.ti.com SBAS430D – JANUARY 2009 – REVISED MAY 2012 TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued) Channel-specific information provided as examples. At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless otherwise noted POWER-SUPPLY CURRENT vs DIGITAL INPUT CODE POWER-SUPPLY CURRENT vs DIGITAL INPUT CODE 1.25 1000 1.20 Power-Supply Current (mA) 1.10 1.05 1.00 0.95 0.90 AVDD = 2.
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DAC7568 DAC8168 DAC8568 SBAS430D – JANUARY 2009 – REVISED MAY 2012 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued) Channel-specific information provided as examples. At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless otherwise noted FULL-SCALE SETTLING TIME: 2.7V RISING EDGE FULL-SCALE SETTLING TIME: 2.
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DAC7568 DAC8168 DAC8568 www.ti.com SBAS430D – JANUARY 2009 – REVISED MAY 2012 TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued) Channel-specific information provided as examples. At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless otherwise noted Channels G/H AVDD AVDD = 2.7V External Reference = 2.5V DAC = Midscale Load = 470pF || 2kW VOUT (20mV/div) POWER-OFF GLITCH Channel D AVDD = 2.
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DAC7568 DAC8168 DAC8568 SBAS430D – JANUARY 2009 – REVISED MAY 2012 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued) Channel-specific information provided as examples. At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless otherwise noted GLITCH ENERGY: 2.7V, 16LSB STEP, RISING EDGE GLITCH ENERGY: 2.7V, 16LSB STEP, FALLING EDGE LDAC/Clock Feedthrough Glitch Impulse ~0.
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DAC7568 DAC8168 DAC8568 www.ti.com SBAS430D – JANUARY 2009 – REVISED MAY 2012 THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER (DAC) VREF The DAC7568, DAC8168, and DAC8568 architecture consists of eight string DACs each followed by an output buffer amplifier. The devices include an internal 2.5V reference with 2ppm/°C temperature drift performance, and offer either 5V or 2.5V full scale output voltage. Figure 120 shows a principal block diagram of the DAC architecture.
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DAC7568 DAC8168 DAC8568 SBAS430D – JANUARY 2009 – REVISED MAY 2012 www.ti.com INTERNAL REFERENCE Enable/Disable Internal Reference The DAC7568, DAC8168, and DAC8568 include a 2.5V internal reference that is disabled by default. The internal reference is externally available at the VREFIN/VREFOUT pin. A minimum 100nF capacitor is recommended between the reference output and GND for noise filtering.
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DAC7568 DAC8168 DAC8568 www.ti.com SBAS430D – JANUARY 2009 – REVISED MAY 2012 Flexible Mode (see Table 4, Table 5, and Table 6) performing a power cycle to reset the device, the internal reference is switched off (default mode). In the default mode, the internal reference is powered down until a valid write sequence is applied to power up the internal reference. When the internal reference is powered up, it remains powered up, regardless of the state of the DACs.
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DAC7568 DAC8168 DAC8568 SBAS430D – JANUARY 2009 – REVISED MAY 2012 SERIAL INTERFACE The DAC7568, DAC8168, and DAC8568 have a 3wire serial interface (SYNC, SCLK, and DIN; see the Pin Configurations) compatible with SPI, QSPI, and Microwire interface standards, as well as most DSPs. See the Serial Write Operation timing diagram (Figure 1) for an example of a typical write sequence.
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DAC7568 DAC8168 DAC8568 www.ti.com SBAS430D – JANUARY 2009 – REVISED MAY 2012 INPUT SHIFT REGISTER DB4), and four additional feature bits. The 16 data bits comprise the 16-, 14-, or 12-bit input code. The input shift register (SR) of the DAC7568, DAC8168, and DAC8568 is 32 bits wide (as shown in The DAC7568, DAC8168, and DAC8568 support a Table 8, Table 9, and Table 10, respectively), and number of different load commands.
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DAC7568 DAC8168 DAC8568 SBAS430D – JANUARY 2009 – REVISED MAY 2012 www.ti.com Table 11.
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DAC7568 DAC8168 DAC8568 www.ti.com SBAS430D – JANUARY 2009 – REVISED MAY 2012 Table 11.
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DAC7568 DAC8168 DAC8568 SBAS430D – JANUARY 2009 – REVISED MAY 2012 www.ti.com Table 11.
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DAC7568 DAC8168 DAC8568 www.ti.com SBAS430D – JANUARY 2009 – REVISED MAY 2012 SYNC INTERRUPT In a normal write sequence, the SYNC line stays low for at least 32 falling edges of SCLK and the addressed DAC register updates on the 32nd falling edge. However, if SYNC is brought high before the 31st falling edge, it acts as an interrupt to the write sequence; the shift register resets and the write sequence is discarded.
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DAC7568 DAC8168 DAC8568 SBAS430D – JANUARY 2009 – REVISED MAY 2012 POWER-DOWN MODES The DAC7568, DAC8168, and DAC8568 have two separate sets of power-down commands. One set is for the DAC channels and the other set is for the internal reference. For more information on powering down the reference, see the Enable/Disable Internal Reference section. DAC Power-Down Commands The DAC7568, DAC8168, and DAC8568 use four modes of operation.
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DAC7568 DAC8168 DAC8568 www.ti.com SBAS430D – JANUARY 2009 – REVISED MAY 2012 CLEAR CODE REGISTER and CLR PIN sequence, this write sequence is aborted and the DAC registers and DAC buffers are cleared as described previously. The DAC7568, DAC8168, and DAC8568 contain a clear code register. The clear code register can be accessed via the serial peripheral interface (SPI) and is user-configurable.
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DAC7568 DAC8168 DAC8568 SBAS430D – JANUARY 2009 – REVISED MAY 2012 www.ti.com OPERATING EXAMPLES: DAC7568/DAC8168/DAC8568 For the following examples X = don't care; value can be either '0' or '1'.
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DAC7568 DAC8168 DAC8568 www.ti.
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DAC7568 DAC8168 DAC8568 SBAS430D – JANUARY 2009 – REVISED MAY 2012 www.ti.com Example 3: Power-Down DAC A, DAC B and DAC H to 1kΩ and Power-Down DAC C, DAC D, and DAC F to 100kΩ DB26 DB25 DB24 DB23 DB22 DB21 DB20 0 0 DB30DB28 Don't Care X DB27 DB31 1st: Write power-down command to DAC channel A and DAC channel B: DAC A and DAC B to 1kΩ.
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DAC7568 DAC8168 DAC8568 www.ti.
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DAC7568 DAC8168 DAC8568 SBAS430D – JANUARY 2009 – REVISED MAY 2012 www.ti.com APPLICATION INFORMATION INTERNAL REFERENCE The internal reference of the DAC7568, DAC8168, and DAC8568 does not require an external load capacitor for stability because it is stable with any capacitive load. However, for improved noise performance, an external load capacitor of 150nF or larger connected to the VREFH/VREFOUT output is recommended.
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DAC7568 DAC8168 DAC8568 www.ti.com SBAS430D – JANUARY 2009 – REVISED MAY 2012 Load Regulation Thermal Hysteresis Load regulation is defined as the change in reference output voltage as a result of changes in load current. The load regulation of the internal reference is measured using force and sense contacts as shown in Figure 126.
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DAC7568 DAC8168 DAC8568 SBAS430D – JANUARY 2009 – REVISED MAY 2012 www.ti.com BIPOLAR OPERATION USING THE DAC7568/DAC8168/DAC8568 The DAC7568, DAC8168, and DAC8568 are designed for single-supply operation, but a bipolar output range is also possible using the circuit in either Figure 127 or Figure 128. The circuit shown gives an output voltage range of ±VREF. Rail-to-rail operation at the amplifier output is achievable using an OPA703 as the output amplifier.
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DAC7568 DAC8168 DAC8568 www.ti.com SBAS430D – JANUARY 2009 – REVISED MAY 2012 MICROPROCESSOR INTERFACING DAC7568/DAC8168/DAC8568 to an 8051 Interface Figure 129 shows a serial interface between the DAC7568, DAC8168, and DAC8568 and a typical 8051-type microcontroller. The setup for the interface is as follows: TXD of the 8051 drives SCLK of the DAC7568, DAC8168, or DAC8568, while RXD drives the serial data line of the device.
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DAC7568 DAC8168 DAC8568 SBAS430D – JANUARY 2009 – REVISED MAY 2012 LAYOUT A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. The DAC7568, DAC8168, and DAC8568 offer singlesupply operation, and are often used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors.
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DAC7568 DAC8168 DAC8568 www.ti.com SBAS430D – JANUARY 2009 – REVISED MAY 2012 PARAMETER DEFINITIONS With the increased complexity of many different specifications listed in product data sheets, this section summarizes selected specifications related to digital-to-analog converters. STATIC PERFORMANCE Static performance parameters are specifications such as differential nonlinearity (DNL) or integral nonlinearity (INL). These are dc specifications and provide information on the accuracy of the DAC.
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DAC7568 DAC8168 DAC8568 SBAS430D – JANUARY 2009 – REVISED MAY 2012 www.ti.com Power-Supply Rejection Ratio (PSRR) Channel-to-Channel DC Crosstalk Power-supply rejection ratio (PSRR) is defined as the ratio of change in output voltage to a change in supply voltage for a full-scale output of the DAC. The PSRR of a device indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is measured in decibels (dB).
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DAC7568 DAC8168 DAC8568 www.ti.com SBAS430D – JANUARY 2009 – REVISED MAY 2012 DAC Output Noise Density Full-Scale Range (FSR) Output noise density is defined as internallygenerated random noise. Random noise is characterized as a spectral density (nV/√Hz). It is measured by loading the DAC to midscale and measuring noise at the output.
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DAC7568 DAC8168 DAC8568 SBAS430D – JANUARY 2009 – REVISED MAY 2012 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (February 20110) to Revision D • Page Changed Logic Input HIGH Voltage parameter test condition into two rows .......................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
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PACKAGE MATERIALS INFORMATION www.ti.com 25-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DAC8168ICPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 DAC8568IAPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 DAC8568IBPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 25-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC8168ICPWR TSSOP PW 16 2000 367.0 367.0 35.0 DAC8568IAPWR TSSOP PW 16 2000 367.0 367.0 35.0 DAC8568IBPWR TSSOP PW 16 2000 367.0 367.0 35.0 DAC8568ICPWR TSSOP PW 16 2000 367.0 367.0 35.0 DAC8568IDPWR TSSOP PW 16 2000 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.