Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - DA converter (DAC) TSSOP 16

Serial Interface

Shift Register

Control

Logic

SCLK

DAC

Latch

DAC

SDIN

GND V

REF

OUT

DAC8581

CLR

DAC8581

www.ti.com

SLAS481C –AUGUST 2005–REVISED OCTOBER 2012

16-BIT, HIGH-SPEED, LOW-NOISE, VOLTAGE OUTPUT

DIGITAL-TO-ANALOG CONVERTER

Check for Samples: DAC8581

FEATURES

APPLICATIONS

• 16-Bit Monotonic

• Industrial Process Control

• ±5-V Bipolar Output • CRT Projection TV Digital Convergence

• Very Low Glitch: 0.5 nV-s • Waveform Generation

• Fast Settling: 0.65 μs • Automated Test Equipment

• Fast Slew Rate: 35 V/μs • Ultrasound

DESCRIPTION

• Low Noise: 20 nV/√Hz

The DAC8581 is a 16-bit, high-speed, low-noise DAC

• ±25-mA Load Drive

operating from dual ±5-V power supplies. The

• ±5-V Dual Power Supply

DAC8581 is monotonic, and has exceptionally low

• Single External Reference

noise and exceptionally low glitch. The DAC8581

high-performance, bipolar output buffer is capable of

• Power-On Reset to Midscale

settling within 0.65 μs for a 10-V step. Small-signal

• 3-MSPS Update Rate

settling time is well under 0.3 μs, supporting data

• SPI™ Interface, Up to 50 MHz

update rates up to 3 MSPS. A power-on-reset circuit

sets the output at midscale voltage on power up.

• 1.8-V–5-V Logic Compatible

• Twos Complement Data Format

The DAC8581 is simple to use, with a single external

reference and a standard 3-wire SPI interface that

• Hardware Reset to Midscale

allows clock rates up to 50 MHz.

• TSSOP-16 Package

Also see the DAC8580, a member of the same

family. The DAC8580 combines DAC8581

performance with an on-chip, 16x over-sampling

digital filter.

The DAC8581 is specified over the –40°C to +85°C

temperature range.

space

FUNCTIONAL BLOCK DIAGRAM OF DAC8581

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2SPI is a trademark of Motorola.

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (19 pages)

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DA C 858 1 DAC8581 www.ti.com SLAS481C – AUGUST 2005 – REVISED OCTOBER 2012 16-BIT, HIGH-SPEED, LOW-NOISE, VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER Check for Samples: DAC8581 FEATURES APPLICATIONS • • • • • • • • • • • • • • • • • • • • • 1 23 16-Bit Monotonic ±5-V Bipolar Output Very Low Glitch: 0.5 nV-s Fast Settling: 0.
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DAC8581 SLAS481C – AUGUST 2005 – REVISED OCTOBER 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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DAC8581 www.ti.com SLAS481C – AUGUST 2005 – REVISED OCTOBER 2012 ELECTRICAL CHARACTERISTICS All specifications at TA = TMIN to TMAX, +AVDD = +5 V, –AVDD = –5 V, DVDD = +5 V (unless otherwise noted). DAC8581 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ±0.03 ±0.1 %FS ±0.25 ±0.5 LSB 2 3 %FS STATIC PERFORMANCE Resolution Linearity error 16 VREF = 4.
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DAC8581 SLAS481C – AUGUST 2005 – REVISED OCTOBER 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = TMIN to TMAX, +AVDD = +5 V, –AVDD = –5 V, DVDD = +5 V (unless otherwise noted). DAC8581 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLY +AVDD 4.0 5 6.0 V –AVDD –4.0 –5 –6.0 V DVDD 1.
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DAC8581 www.ti.
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DAC8581 SLAS481C – AUGUST 2005 – REVISED OCTOBER 2012 www.ti.com TYPICAL CHARACTERISTICS LINEARITY ERROR vs INPUT CODE DIFFERENTIAL LINEARITY ERROR vs INPUT CODE 20 0.5 15 10 DLE − LSBs 0.25 LE − LSBs 5 0 −5 −10 0 −0.25 −15 −20 −0.5 0 8192 16384 24576 32768 40960 49152 57344 8192 0 65536 16384 24576 Input Code 30 INTEGRAL NONLINEARITY ERROR vs SUPPLY VOLTAGE 65536 30 AVDD = 6 V, AVSS = −6 V 20 10 AVSS = −AVDD, VREF = AVDD −0.
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DAC8581 www.ti.com SLAS481C – AUGUST 2005 – REVISED OCTOBER 2012 TYPICAL CHARACTERISTICS (continued) POSITIVE SUPPLY CURRENT—IDD vs TEMPERATURE NEGATIVE SUPPLY CURRENT—ISS vs TEMPERATURE 25 I SS − Supply Current − mA IDD − Supply Current − mA −11 20 15 −13 −15 −17 −19 −21 −23 10 −40 −20 0 20 40 60 −25 −40 80 TA − Free-Air Temperature − °C 20 40 60 80 Figure 8. Figure 9. POSITIVE SUPPLY CURRENT—IDD vs CODE NEGATIVE SUPPLY CURRENT—ISS vs CODE −19.5 I SS − Supply Current − mA 14.
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DAC8581 SLAS481C – AUGUST 2005 – REVISED OCTOBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) DIGITAL FEEDTHROUGH AND MIDCODE GLITCH OUTPUT VOLTAGE NOISE 100 k Hz V n − Output Noise Voltage − nV/ mV − 10 mV/div Glitch Feedthrough FSYNC 10 k 1k 100 10 1 t − Time − 1µs 10 100 1k 10 k 100 k f − Frequency − Hz Figure 14. Figure 15.
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DAC8581 www.ti.com SLAS481C – AUGUST 2005 – REVISED OCTOBER 2012 THEORY OF OPERATION The DAC8581 uses a proprietary, monotonic, high-speed resistor string architecture. The 16-bit input data are coded in twos complement, MSB-first format and transmitted using a 3-wire serial interface. The serial interface sends the input data to the DAC latch. The digital data are then decoded to select a tap voltage of the resistor string. The resistor string output is sent to a high-performance output amplifier.
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DAC8581 SLAS481C – AUGUST 2005 – REVISED OCTOBER 2012 www.ti.com Glitch area is low at 0.5 nV-s, with peak glitch amplitude under 10 mV, and the glitch duration under 100 ns. Low glitch is obtained for code-to-code (small signal) changes across the entire transfer function of the device. For large signals, settling characteristics of the reference and output amplifiers are observed in terms of overshoot and undershoot.
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DAC8581 www.ti.com SLAS481C – AUGUST 2005 – REVISED OCTOBER 2012 APPLICATION INFORMATION IMPROVING DAC8581 LINEARITY USING EXTERNAL CALIBRATION At output frequencies up to 50 kHz, DAC8581 linearity error and total harmonic distortion are dominated by resistor mismatches in the string. These resistor mismatches are fairly insensitive to temperature and aging effects and also to reference voltage changes.
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DAC8581 SLAS481C – AUGUST 2005 – REVISED OCTOBER 2012 www.ti.com Ideal−DAC Transfer Curve Main −DAC Transfer Curve VI2 PWL Segment VI0 VI0B VI1 I0 I0B I1 I2 Figure 21. The Geometry Behind the PWL Calibration I0 + I1 ) (I2 * I1)(D0 * VI1) VI2 * VI1 (1) Where both x-axis and y-axis are normalized from 0 to 65535, and: VI0: Desired ideal DAC voltage corresponding to input code D0. VI0B: DAC8581 output voltage, which approximates VI0 after PWL calibration.
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DAC8581 www.ti.com SLAS481C – AUGUST 2005 – REVISED OCTOBER 2012 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (August, 2005) to Revision B Page • Updated document format to current stylistic standards ...................................................................................................... 1 • Deleted lead temperature specifications from Absolute Maximum Ratings table ..............................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 5-Oct-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device DAC8581IPWR Package Package Pins Type Drawing TSSOP PW 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 12.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) 5.6 1.6 8.0 W Pin1 (mm) Quadrant 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 5-Oct-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC8581IPWR TSSOP PW 16 2000 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.