DAC8718 DA C 871 8 DA C8 71 8 www.ti.com SBAS467A – MAY 2009 – REVISED DECEMBER 2009 Octal, 16-Bit, Low-Power, High-Voltage Output, Serial Input DIGITAL-TO-ANALOG CONVERTER Check for Samples: DAC8718 FEATURES DESCRIPTION • • • • • • The DAC8718 is a low-power, octal, 16-bit digital-to-analog converter (DAC). With a 5V reference, the output can either be a bipolar ±15V voltage when operating from dual ±15.5V (or higher) power supplies, or a unipolar 0V to +30V voltage when operating from a +30.
DAC8718 SBAS467A – MAY 2009 – REVISED DECEMBER 2009 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
DAC8718 www.ti.com SBAS467A – MAY 2009 – REVISED DECEMBER 2009 ELECTRICAL CHARACTERISTICS: Dual-Supply All specifications at TA = TMIN to TMAX, AVDD = +16.5V, AVSS = –16.5V, IOVDD = DVDD = +5V, REF-A and REF-B = +5V, gain = 6, AGND-x = DGND = 0V, data format = straight binary, and Offset DAC A and Offset DAC B are at default values (1), unless otherwise noted.
DAC8718 SBAS467A – MAY 2009 – REVISED DECEMBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS: Dual-Supply (continued) All specifications at TA = TMIN to TMAX, AVDD = +16.5V, AVSS = –16.5V, IOVDD = DVDD = +5V, REF-A and REF-B = +5V, gain = 6, AGND-x = DGND = 0V, data format = straight binary, and Offset DAC A and Offset DAC B are at default values (1), unless otherwise noted.
DAC8718 www.ti.com SBAS467A – MAY 2009 – REVISED DECEMBER 2009 ELECTRICAL CHARACTERISTICS: Dual-Supply (continued) All specifications at TA = TMIN to TMAX, AVDD = +16.5V, AVSS = –16.5V, IOVDD = DVDD = +5V, REF-A and REF-B = +5V, gain = 6, AGND-x = DGND = 0V, data format = straight binary, and Offset DAC A and Offset DAC B are at default values (1), unless otherwise noted.
DAC8718 SBAS467A – MAY 2009 – REVISED DECEMBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS: Dual-Supply (continued) All specifications at TA = TMIN to TMAX, AVDD = +16.5V, AVSS = –16.5V, IOVDD = DVDD = +5V, REF-A and REF-B = +5V, gain = 6, AGND-x = DGND = 0V, data format = straight binary, and Offset DAC A and Offset DAC B are at default values (1), unless otherwise noted. DAC8718 PARAMETER CONDITIONS MIN TYP MAX UNIT POWER SUPPLY AVDD +4.5 +18 V AVSS –18 –4.5 V DVDD +2.7 +5.
DAC8718 www.ti.com SBAS467A – MAY 2009 – REVISED DECEMBER 2009 ELECTRICAL CHARACTERISTICS: Single-Supply All specifications at TA = TMIN to TMAX, AVDD = +32V, AVSS = 0V, IOVDD = DVDD = +5V, REF-A and REF-B = +5V, gain = 6, AGND-x = DGND = 0V, data format = straight binary, and OFFSET-A = OFFSET-B = AGND, unless otherwise noted.
DAC8718 SBAS467A – MAY 2009 – REVISED DECEMBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS: Single-Supply (continued) All specifications at TA = TMIN to TMAX, AVDD = +32V, AVSS = 0V, IOVDD = DVDD = +5V, REF-A and REF-B = +5V, gain = 6, AGND-x = DGND = 0V, data format = straight binary, and OFFSET-A = OFFSET-B = AGND, unless otherwise noted.
DAC8718 www.ti.com SBAS467A – MAY 2009 – REVISED DECEMBER 2009 ELECTRICAL CHARACTERISTICS: Single-Supply (continued) All specifications at TA = TMIN to TMAX, AVDD = +32V, AVSS = 0V, IOVDD = DVDD = +5V, REF-A and REF-B = +5V, gain = 6, AGND-x = DGND = 0V, data format = straight binary, and OFFSET-A = OFFSET-B = AGND, unless otherwise noted. DAC8718 PARAMETER CONDITIONS MIN TYP MAX UNIT IOVDD – 0.4 IOVDD V 1.6 IOVDD V DIGITAL OUTPUT (17) High-level output voltage, VOH (SDO) IOVDD = +2.7V to +5.
DAC8718 SBAS467A – MAY 2009 – REVISED DECEMBER 2009 www.ti.
DAC8718 www.ti.
DAC8718 SBAS467A – MAY 2009 – REVISED DECEMBER 2009 www.ti.com PIN DESCRIPTIONS (continued) PIN NAME QFN-48 TQFP-64 I/O DVDD 17 24 I Digital power supply DGND 20 25 I Digital ground DGND 22 28 I Digital ground GPIO-1 23 29 I/O General-purpose digital input/output 1. This pin is a bidirectional digital input/output, open-drain and requires an external resistor. See the GPIO Pins section for details. GPIO-0 24 30 I/O General-purpose digital input/output 0.
DAC8718 www.ti.com SBAS467A – MAY 2009 – REVISED DECEMBER 2009 TIMING DIAGRAMS Case 1: Standalone mode: Update without LDAC pin; LDAC pin tied to logic low. t8 t4 CS t7 t1 Input Data Register and DAC Latch Updated When Correction Completes(1) SCLK t2 t5 t6 BIT 22 BIT 23 (MSB) SDI LDAC t3 BIT 1 BIT 0 Low NOTE: (1) If the correction engine is off, the DAC latch is reloaded immediately after the DAC Data Register is updated. Case 2: Standalone mode: Update with LDAC pin.
DAC8718 SBAS467A – MAY 2009 – REVISED DECEMBER 2009 www.ti.com TIMING DIAGRAMS (continued) Case 3: Daisy-Chain Mode: Update without LDAC pin; LDAC pin tied to logic low.
DAC8718 www.ti.com SBAS467A – MAY 2009 – REVISED DECEMBER 2009 TIMING DIAGRAMS (continued) Case 6: Readback for Standalone mode. t8 t4 t7 CS Internal Register Updated t1 SCLK t2 t3 t5 BIT 23 (= 1) SDI t6 BIT 22 BIT 0 BIT 23 (= 1) t13 Input Word Specifies Register to be Read SDO LDAC Hi-Z Hi-Z t11 BIT 23 BIT 22 BIT 1 BIT 0 NOP Command (write ‘1’ to NOP bit) BIT 22 BIT 1 BIT 0 Hi-Z Data from the Selected Register Low = Don’t Care Bit 23 = MSB Bit 0 = LSB Figure 4.
DAC8718 SBAS467A – MAY 2009 – REVISED DECEMBER 2009 www.ti.com TIMING CHARACTERISTICS: IOVDD = +5V (1) (2) (3) (4) At –40°C to +105°C, DVDD = +5V, and IOVDD = +5V, unless otherwise noted.
DAC8718 www.ti.com SBAS467A – MAY 2009 – REVISED DECEMBER 2009 TIMING CHARACTERISTICS: IOVDD = +1.8V (1) (2) (3) (4) At –40°C to +105°C, DVDD = +3V/+5V, and IOVDD = +1.8V, unless otherwise noted. PARAMETER MIN MAX UNIT 16.
DAC8718 SBAS467A – MAY 2009 – REVISED DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS: Bipolar At TA = 25°C, AVDD = 16.5V, AVSS = –16.5V, VREF = IOVDD = DVDD = 5V, gain = 6, data format=USB, unless otherwise noted. LINEARITY ERROR vs DIGITAL INPUT CODE (All 8 Channels) DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (All 8 Channels) 1.0 4 All Eight Channels Shown 0.6 DNL Error (LSB) 2 INL Error (LSB) All Eight Channels Shown 0.8 3 1 0 -1 0.4 0.2 0 -0.2 -0.4 -2 -0.6 -3 -0.8 -1.
DAC8718 www.ti.com SBAS467A – MAY 2009 – REVISED DECEMBER 2009 TYPICAL CHARACTERISTICS: Bipolar (continued) At TA = 25°C, AVDD = 16.5V, AVSS = –16.5V, VREF = IOVDD = DVDD = 5V, gain = 6, data format=USB, unless otherwise noted. LINEARITY ERROR vs DIGITAL INPUT CODE (–40°C) DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (–40°C) 4 1.0 Typical Channel Shown 0.6 DNL Error (LSB) 2 INL Error (LSB) Typical Channel Shown 0.8 3 1 0 -1 0.4 0.2 0 -0.2 -0.4 -2 -0.6 -3 -0.8 -4 -1.
DAC8718 SBAS467A – MAY 2009 – REVISED DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS: Bipolar (continued) At TA = 25°C, AVDD = 16.5V, AVSS = –16.5V, VREF = IOVDD = DVDD = 5V, gain = 6, data format=USB, unless otherwise noted. LINEARITY ERROR vs TEMPERATURE 4 1.0 3 0.8 0.6 DNL Error (LSB) INL Max 2 INL Error (LSB) DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE 1 0 INL Min -1 0 -0.2 DNL Min -0.4 -0.6 -3 -0.8 -1.
DAC8718 www.ti.com SBAS467A – MAY 2009 – REVISED DECEMBER 2009 TYPICAL CHARACTERISTICS: Bipolar (continued) At TA = 25°C, AVDD = 16.5V, AVSS = –16.5V, VREF = IOVDD = DVDD = 5V, gain = 6, data format=USB, unless otherwise noted. LINEARITY ERROR vs AVDD AND AVSS 4 1.0 DVDD = IOVDD = 4.5V VREF = 2.048V Gain = 4 3 2 0.6 INL Max 1 0 INL Min -1 DVDD = IOVDD = 4.5V VREF = 2.048V Gain = 4 0.8 DNL Error (LSB) INL Error (LSB) DIFFERENTIAL LINEARITY ERROR vs AVDD AND AVSS DNL Max 0.4 0.2 0 -0.
DAC8718 SBAS467A – MAY 2009 – REVISED DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS: Bipolar (continued) At TA = 25°C, AVDD = 16.5V, AVSS = –16.5V, VREF = IOVDD = DVDD = 5V, gain = 6, data format=USB, unless otherwise noted. BIPOLAR GAIN ERROR vs REFERENCE VOLTAGE BIPOLAR GAIN ERROR vs REFERENCE VOLTAGE 5 5 AVDD = +18V AVSS = -18V 3 2 1 0 -1 -2 Ch4 Ch5 Ch6 Ch7 Ch0 Ch1 Ch2 Ch3 -3 -4 1.5 2.0 2.5 3.0 3.5 VREF (V) 4.0 4.5 5.0 -2 3.0 3.5 VREF (V) 4.0 BIPOLAR ZERO ERROR vs TEMPERATURE 4.
DAC8718 www.ti.com SBAS467A – MAY 2009 – REVISED DECEMBER 2009 TYPICAL CHARACTERISTICS: Bipolar (continued) At TA = 25°C, AVDD = 16.5V, AVSS = –16.5V, VREF = IOVDD = DVDD = 5V, gain = 6, data format=USB, unless otherwise noted. ANALOG POWER-SUPPLY CURRENT vs TEMPERATURE ANALOG POWER-SUPPLY CURRENT vs REFERENCE VOLTAGE 8 Analog Power-Supply Current (mA) Analog Power-Supply Current (mA) 8 7 6 IAVDD 5 4 -IAVSS 3 2 1 0 5 20 35 50 65 Temperature (°C) 80 95 110 125 5 IAVDD 4 3 2 -IAVSS 1 1.0 1.
DAC8718 SBAS467A – MAY 2009 – REVISED DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS: Bipolar (continued) At TA = 25°C, AVDD = 16.5V, AVSS = –16.5V, VREF = IOVDD = DVDD = 5V, gain = 6, data format=USB, unless otherwise noted.
DAC8718 www.ti.com SBAS467A – MAY 2009 – REVISED DECEMBER 2009 TYPICAL CHARACTERISTICS: Bipolar (continued) At TA = 25°C, AVDD = 16.5V, AVSS = –16.5V, VREF = IOVDD = DVDD = 5V, gain = 6, data format=USB, unless otherwise noted.
DAC8718 SBAS467A – MAY 2009 – REVISED DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS: Bipolar (continued) At TA = 25°C, AVDD = 16.5V, AVSS = –16.5V, VREF = IOVDD = DVDD = 5V, gain = 6, data format=USB, unless otherwise noted. VOUT (5mV/div) DAC OUTPUT NOISE 0.1Hz TO 10Hz VOUT (5mV/div) DAC OUTPUT NOISE 0.1Hz TO 10Hz DAC Code = 8000h No Load Gain = 6 Channel 0 as Example Time (2ms/div) Time (2ms/div) Figure 51. 26 DAC Code = 8000h No Load Gain = 4 Channel 0 as Example Figure 52.
DAC8718 www.ti.com SBAS467A – MAY 2009 – REVISED DECEMBER 2009 TYPICAL CHARACTERISTICS: Unipolar At TA = 25°C, AVDD = 32V, AVSS = 0V, VREF = 5V, IOVDD = DVDD = 5V, gain=6, and data format=USB, unless otherwise noted. LINEARITY ERROR vs DIGITAL INPUT CODE (All 8 Channels) DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (All 8 Channels) 1.0 4 All Eight Channels Shown 0.6 DNL Error (LSB) 2 INL Error (LSB) All Eight Channels Shown 0.8 3 1 0 -1 0.4 0.2 0 -0.2 -0.4 -2 -0.6 -3 -0.8 -1.
DAC8718 SBAS467A – MAY 2009 – REVISED DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS: Unipolar (continued) At TA = 25°C, AVDD = 32V, AVSS = 0V, VREF = 5V, IOVDD = DVDD = 5V, gain=6, and data format=USB, unless otherwise noted. LINEARITY ERROR vs DIGITAL INPUT CODE (–40°C) DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (–40°C) 4 1.0 Typical Channel Shown 0.6 DNL Error (LSB) 2 INL Error (LSB) Typical Channel Shown 0.8 3 1 0 -1 0.4 0.2 0 -0.2 -0.4 -2 -0.6 -3 -0.8 -4 -1.
DAC8718 www.ti.com SBAS467A – MAY 2009 – REVISED DECEMBER 2009 TYPICAL CHARACTERISTICS: Unipolar (continued) At TA = 25°C, AVDD = 32V, AVSS = 0V, VREF = 5V, IOVDD = DVDD = 5V, gain=6, and data format=USB, unless otherwise noted. LINEARITY ERROR vs TEMPERATURE 4 1.0 3 0.8 0.6 DNL Error (LSB) INL Max 2 INL Error (LSB) DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE 1 0 -1 INL Min DNL Max 0.4 0.2 0 -0.2 DNL Min -0.4 -2 -0.6 -3 -0.8 -1.
DAC8718 SBAS467A – MAY 2009 – REVISED DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS: Unipolar (continued) At TA = 25°C, AVDD = 32V, AVSS = 0V, VREF = 5V, IOVDD = DVDD = 5V, gain=6, and data format=USB, unless otherwise noted. LINEARITY ERROR vs ANALOG SUPPLY VOLTAGE DIFFERENTIAL LINEARITY ERROR vs ANALOG SUPPLY VOLTAGE 4 1.0 3 0.8 INL Max DNL Error (LSB) INL Error (LSB) DNL Max 0.6 2 1 0 INL Min -1 0.4 0.2 0 -0.2 DNL Min -0.4 -2 -0.6 -3 -0.8 -4 -1.
DAC8718 www.ti.com SBAS467A – MAY 2009 – REVISED DECEMBER 2009 TYPICAL CHARACTERISTICS: Unipolar (continued) At TA = 25°C, AVDD = 32V, AVSS = 0V, VREF = 5V, IOVDD = DVDD = 5V, gain=6, and data format=USB, unless otherwise noted. UNIPOLAR GAIN ERROR vs REFERENCE VOLTAGE 5 Ch0 Ch1 Ch2 Ch3 3 2 5 AVDD = +36V Ch4 Ch5 Ch6 Ch7 1 0 -1 -2 -3 -4 2 1 0 -1 -2 -3 -5 1.0 1.5 2.0 2.5 3.0 3.5 VREF (V) 4.0 4.5 5.0 5.5 1.0 1.5 2.0 2.5 3.0 3.5 VREF (V) 4.0 Figure 75. Figure 76.
DAC8718 SBAS467A – MAY 2009 – REVISED DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS: Unipolar (continued) At TA = 25°C, AVDD = 32V, AVSS = 0V, VREF = 5V, IOVDD = DVDD = 5V, gain=6, and data format=USB, unless otherwise noted.
DAC8718 www.ti.com SBAS467A – MAY 2009 – REVISED DECEMBER 2009 TYPICAL CHARACTERISTICS: Unipolar (continued) At TA = 25°C, AVDD = 32V, AVSS = 0V, VREF = 5V, IOVDD = DVDD = 5V, gain=6, and data format=USB, unless otherwise noted.
DAC8718 SBAS467A – MAY 2009 – REVISED DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS: Unipolar (continued) At TA = 25°C, AVDD = 32V, AVSS = 0V, VREF = 5V, IOVDD = DVDD = 5V, gain=6, and data format=USB, unless otherwise noted.
DAC8718 www.ti.com SBAS467A – MAY 2009 – REVISED DECEMBER 2009 THEORY OF OPERATION GENERAL DESCRIPTION The DAC8718 contains eight DAC channels and eight output amplifiers in a single package. Each channel consists of a resistor-string DAC followed by an output buffer amplifier. The resistor-string section is simply a string of resistors, each with a value of R, from REF-x to AGND, as shown in Figure 97. This type of architecture provides DAC monotonicity.
DAC8718 SBAS467A – MAY 2009 – REVISED DECEMBER 2009 www.ti.com USER-CALIBRATION FOR ZERO-CODE ERROR AND GAIN ERROR The DAC8718 implements a digital user-calibration function that allows for trimming gain and zero errors on the entire signal chain. This function can eliminate the need for external adjustment circuits. Each DAC channel has a Zero Register and Gain Register.
DAC8718 www.ti.
DAC8718 SBAS467A – MAY 2009 – REVISED DECEMBER 2009 www.ti.com INPUT DATA FORMAT The USB/BTC pin defines the input data format and the Offset DAC format. When this pin is connected to DGND, the Input DAC data and Offset DAC data are straight binary, as shown in Table 1 and Table 3. When this pin is connected to IOVDD, the Input DAC data and Offset DAC data are in twos complement format, as shown in Table 2 and Table 4. Table 1.
DAC8718 www.ti.com SBAS467A – MAY 2009 – REVISED DECEMBER 2009 OFFSET DACS There are two 16-bit Offset DACs: one for Group A, and one for Group B. The Offset DACs allow the entire output curve of the associated DAC groups to be shifted by introducing a programmable offset. This offset allows for asymmetric bipolar operation of the DACs or unipolar operation with bipolar supplies.
DAC8718 SBAS467A – MAY 2009 – REVISED DECEMBER 2009 www.ti.com VOUT = GAIN x V1 - (GAIN - 1) x VOFF DAC Channel V1 VOUT AGND-x Offset DAC VOFF OFFSET Figure 98. Output Amplifier and Offset DAC OUTPUT AMPLIFIERS The output amplifiers can swing to 0.5V below the positive supply and 0.5V above the negative supply. This condition limits how much the output can be offset for a given reference voltage. The maximum range of the output for ±17V power and a +5.5V reference is –16.5V to +16.5V for gain = 6.
DAC8718 www.ti.com SBAS467A – MAY 2009 – REVISED DECEMBER 2009 GENERAL-PURPOSE INPUT/OUTPUT PINS (GPIO-0 to GPIO-2) The GPIO pins are general-purpose, bidirectional, digital input/outputs, as shown in Figure 99. When a GPIO pin acts as an output, the pin status is determined by the corresponding GPIO bit in the GPIO Register. The pin output is high-impedance when the GPIO bit is set to '1', and is logic low when the GPIO bit is cleared to '0'.
DAC8718 SBAS467A – MAY 2009 – REVISED DECEMBER 2009 www.ti.com POWER-ON RESET The DAC8718 contains a power-on reset circuit that controls the output during power-on and power down. This feature is useful in applications where the known state of the DAC output during power-on is important. The Offset DAC Registers, DAC Data Registers, and DAC latches are loaded with the value defined by the RSTSEL pin, as shown in Table 7. The Gain Registers and Zero Registers are loaded with default values.
DAC8718 www.ti.com SBAS467A – MAY 2009 – REVISED DECEMBER 2009 UPDATING THE DAC OUTPUTS Depending on the status of both CS and LDAC, and after data have been transferred into the DAC Data registers, the DAC outputs can be updated either in asynchronous mode or synchronous mode. This update mode is established at power-on. If asynchronous mode is desired, the LDAC pin must be permanently tied low before power is applied to the device.
DAC8718 SBAS467A – MAY 2009 – REVISED DECEMBER 2009 www.ti.com MONITOR OUTPUT PIN (VMON) The VMON pin is the channel monitor output. It can be either high-impedance or monitor any one of the DAC outputs, auxiliary analog inputs, offset DAC outputs, or reference buffer outputs.
DAC8718 www.ti.com SBAS467A – MAY 2009 – REVISED DECEMBER 2009 SERIAL INTERFACE The DAC8718 is controlled over a versatile, three-wire serial interface that operates at clock rates of up to 50MHz and is compatible with SPI, QSPI™, Microwire™, and DSP™ standards. SPI Shift Register The SPI Shift Register is 24 bits wide. Data are loaded into the device MSB first as a 24-bit word under the control of the serial clock input, SCLK.
DAC8718 SBAS467A – MAY 2009 – REVISED DECEMBER 2009 www.ti.com Shift Register, thus greatly speeding up the data transfer. For example, consider three DAC8718s (A, B, and C) in a daisy-chain configuration. The data from the SPI controller are transferred first to A, then to B, and finally to C. In normal daisy-chain operation, a total of 72 clocks are needed to transfer one word to C.
DAC8718 www.ti.com SBAS467A – MAY 2009 – REVISED DECEMBER 2009 SPI SHIFT REGISTER The SPI Shift Register is 24 bits wide, as shown in Table 9. The register mapping is shown in Table 10; X = don't care—writing to it has no effect, reading it returns '0'. Table 9. Shift Register Format MSB DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15:DB0 R/W X X A4 A3 A2 A1 A0 DATA R/W Indicates a read from or a write to the addressed register.
DAC8718 SBAS467A – MAY 2009 – REVISED DECEMBER 2009 www.ti.com Table 10.
DAC8718 www.ti.com SBAS467A – MAY 2009 – REVISED DECEMBER 2009 INTERNAL REGISTERS The DAC8718 internal registers consist of the Configuration Register, the Monitor Register, the DAC Input Data Registers, the Zero Registers, the DAC Data Registers, and the Gain Registers, and are described in the following section. The Configuration Register specifies which actions are performed by the device. Table 11 shows the details. Table 11.
DAC8718 SBAS467A – MAY 2009 – REVISED DECEMBER 2009 www.ti.com Monitor Register (default = 0000h). The Monitor Register selects one of the DAC outputs, auxiliary analog inputs, reference buffer outputs, or offset DAC outputs to be monitored through the VMON pin. When bits [D15:D4] = '0', the monitor is disabled and VMON is in a Hi-Z state.
DAC8718 www.ti.com SBAS467A – MAY 2009 – REVISED DECEMBER 2009 Offset DAC-A/B Registers (default = 999Ah for dual supplies or 0000h for single supplies). The Offset DAC-A and Offset DAC-B registers contain, by default, the factory-trimmed Offset DAC code providing optimal offset and span for symmetric bipolar operation when dual supplies are detected, and contain code 0000h when a single supply is detected.
DAC8718 SBAS467A – MAY 2009 – REVISED DECEMBER 2009 www.ti.com Zero Register n, where n = 0 to 7 (default = 0000h). The Zero Register stores the user-calibration data that are used to eliminate the offset error. The data are 16 bits wide, 1 LSB/step, and the total adjustment is –32768 LSB to +32767 LSB, or ±50% of full-scale range. The Zero Register uses a twos complement data format. Table 14.
DAC8718 www.ti.
DAC8718 SBAS467A – MAY 2009 – REVISED DECEMBER 2009 www.ti.com PRECISION VOLTAGE REFERENCE SELECTION To achieve the optimum performance from the DAC8718 over the full operating temperature range, a precision voltage reference must be used. Careful consideration should be given to the selection of a precision voltage reference. The DAC8718 has two reference inputs, REF-A and REF-B. The voltages applied to the reference inputs are used to provide a buffered positive reference for the DAC cores.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DAC8718SPAGR TQFP PAG 64 1500 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2 DAC8718SRGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 DAC8718SRGZT VQFN RGZ 48 250 330.0 16.4 7.3 7.3 1.5 12.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC8718SPAGR TQFP PAG 64 1500 367.0 367.0 45.0 DAC8718SRGZR VQFN RGZ 48 2500 336.6 336.6 28.6 DAC8718SRGZT VQFN RGZ 48 250 336.6 336.6 28.
MECHANICAL DATA MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996 PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 48 0,08 M 33 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 1,05 0,95 0°– 7° 0,75 0,45 Seating Plane 0,08 1,20 MAX 4040282 / C 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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