DA C8 728 DAC8728 DA C8 728 www.ti.com SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 Octal, 16-Bit, Low-Power, High-Voltage Output, Parallel Input DIGITAL-TO-ANALOG CONVERTER Check for Samples: DAC8728 FEATURES DESCRIPTION • • • • • • • The DAC8728 is a low-power, octal, 16-bit digital-to-analog converter (DAC). With a 5V reference, the output can either be a bipolar ±15V voltage when operating from a dual ±15.
DAC8728 SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
DAC8728 www.ti.com SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 ELECTRICAL CHARACTERISTICS: Dual-Supply All specifications at TA = TMIN to TMAX, AVDD = +16.5V, AVSS = –16.5V, DVDD = +5V, REF-A and REF-B = +5V, gain = 6, AGND-x = DGND = 0V, and Offset DAC A and Offset DAC B are at default values (1), unless otherwise noted.
DAC8728 SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS: Dual-Supply (continued) All specifications at TA = TMIN to TMAX, AVDD = +16.5V, AVSS = –16.5V, DVDD = +5V, REF-A and REF-B = +5V, gain = 6, AGND-x = DGND = 0V, and Offset DAC A and Offset DAC B are at default values (1), unless otherwise noted. DAC8728 PARAMETER CONDITIONS MIN TYP MAX UNIT V ANALOG OUTPUT (VOUT-0 to VOUT-7) (3) Voltage output (4) Output impedance VREF = +5V –15 +15 VREF = +1.5V –4.
DAC8728 www.ti.com SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 ELECTRICAL CHARACTERISTICS: Dual-Supply (continued) All specifications at TA = TMIN to TMAX, AVDD = +16.5V, AVSS = –16.5V, DVDD = +5V, REF-A and REF-B = +5V, gain = 6, AGND-x = DGND = 0V, and Offset DAC A and Offset DAC B are at default values (1), unless otherwise noted.
DAC8728 SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS: Dual-Supply (continued) All specifications at TA = TMIN to TMAX, AVDD = +16.5V, AVSS = –16.5V, DVDD = +5V, REF-A and REF-B = +5V, gain = 6, AGND-x = DGND = 0V, and Offset DAC A and Offset DAC B are at default values (1), unless otherwise noted. DAC8728 PARAMETER CONDITIONS MIN TYP MAX UNIT POWER SUPPLY AVDD +4.5 +18 V AVSS –18 –4.5 V DVDD +2.7 +5.5 V IOVDD +1.
DAC8728 www.ti.com SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 ELECTRICAL CHARACTERISTICS: Single-Supply All specifications at TA = TMIN to TMAX, AVDD = +32V, AVSS = 0V, DVDD = +5V, REF-A and REF-B = +5V, gain = 6, AGND-x = DGND = 0V, and OFFSET-A = OFFSET-B = AGND, unless otherwise noted.
DAC8728 SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS: Single-Supply (continued) All specifications at TA = TMIN to TMAX, AVDD = +32V, AVSS = 0V, DVDD = +5V, REF-A and REF-B = +5V, gain = 6, AGND-x = DGND = 0V, and OFFSET-A = OFFSET-B = AGND, unless otherwise noted.
DAC8728 www.ti.com SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 ELECTRICAL CHARACTERISTICS: Single-Supply (continued) All specifications at TA = TMIN to TMAX, AVDD = +32V, AVSS = 0V, DVDD = +5V, REF-A and REF-B = +5V, gain = 6, AGND-x = DGND = 0V, and OFFSET-A = OFFSET-B = AGND, unless otherwise noted. DAC8728 PARAMETER CONDITIONS MIN TYP MAX UNIT POWER SUPPLY AVDD +9 +36 V DVDD +2.7 +5.5 V IOVDD +1.7 DVDD AIDD DIDD IOIDD Power dissipation 4.
DAC8728 SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.
DAC8728 www.ti.com SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 PIN DESCRIPTIONS (continued) PIN NAME (2) PIN NO. QFN-56 TQFP-64 I/O DESCRIPTION LDAC 17 18 I Load DAC latch control input (active low). When LDAC is low, the DAC latch is transparent and the contents of the DAC Data Register are transferred to it. The DAC output changes to the corresponding level simultaneously when the DAC latch is updated. See the DAC Output Update section for details.
DAC8728 SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.com TIMING DIAGRAMS t8 t1 CS t9 CS t10 t2 t3 R/W R/W t12 t11 t13 D15:D0 t5 t4 A4:A0 A4:A0 t14 Hi-Z Hi-Z Hi-Z D15:D0 Hi-Z t6 Figure 2. Read Operation t7 Write Operation 1: 1. Writing to the Configuration Register, Offset Register, Monitor Register, GPIO Register. 2. Writing to the DAC Input Registers, Zero Registers, and Gain Registers in Asynchronous mode (LDAC pin is tied low). Figure 3.
DAC8728 www.ti.com SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 TIMING CHARACTERISTICS (1) (2) (3) (4) (5) At –40°C to +105°C, DVDD = +5V to +5.5V, and IOVDD = +5V, unless otherwise noted.
DAC8728 SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 TIMING CHARACTERISTICS (1) www.ti.com (2) (3) (4) (5) At –40°C to +105°C, DVDD = +3V to +5V, and IOVDD = +3V, unless otherwise noted.
DAC8728 www.ti.com SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 TIMING CHARACTERISTICS (1) (2) (3) (4) (5) At –40°C to +105°C, DVDD = +3V to +5V, and IOVDD = +1.8V, unless otherwise noted.
DAC8728 SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS: Dual-Supply At TA = +25°C, VREF = +5V, AVDD = +16.5V, AVSS = –16.5V, and gain = 6, unless otherwise noted. LINEARITY ERROR vs DIGITAL INPUT CODE 4 DAC0 DAC1 DAC2 DAC3 TA = +25°C 3 1.00 DAC4 DAC5 DAC6 DAC7 1 0 -1 0.50 0.25 0 -0.25 -2 -0.50 -3 -0.75 -4 DAC0 DAC1 DAC2 DAC3 -1.
DAC8728 www.ti.com SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 TYPICAL CHARACTERISTICS: Dual-Supply (continued) At TA = +25°C, VREF = +5V, AVDD = +16.5V, AVSS = –16.5V, and gain = 6, unless otherwise noted. LINEARITY ERROR vs DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 4 1.00 TA = -40°C 3 0.50 DNL Error (LSB) INL Error (LSB) 2 1 0 -1 0 -0.25 -0.50 -3 -0.75 -1.
DAC8728 SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS: Dual-Supply (continued) At TA = +25°C, VREF = +5V, AVDD = +16.5V, AVSS = –16.5V, and gain = 6, unless otherwise noted. LINEARITY ERROR vs TEMPERATURE 4 1.00 3 0.75 2 DNL Max 0.50 INL Max DNL Error (LSB) INL Error (LSB) DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE 1 0 INL Min -1 0.25 0 -0.25 -2 -0.50 -3 -0.75 -4 DNL Min -1.
DAC8728 www.ti.com SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 TYPICAL CHARACTERISTICS: Dual-Supply (continued) At TA = +25°C, VREF = +5V, AVDD = +16.5V, AVSS = –16.5V, and gain = 6, unless otherwise noted.
DAC8728 SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS: Dual-Supply (continued) At TA = +25°C, VREF = +5V, AVDD = +16.5V, AVSS = –16.5V, and gain = 6, unless otherwise noted. BIPOLAR ZERO ERROR vs AVDD AND AVSS GAIN ERROR vs AVDD AND AVSS 5 5 VREF = 2.048V Gain = 4 3 3 2 2 1 0 -1 -2 DAC0 DAC1 DAC2 DAC3 -3 -4 1 0 -1 -2 DAC4 DAC5 DAC6 DAC7 DAC0 DAC1 DAC2 DAC3 -3 -4 -5 6 8 10 12 AVDD = -AVSS (V) 14 16 18 4 6 8 10 12 AVDD = -AVSS (V) Figure 29.
DAC8728 www.ti.com SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 TYPICAL CHARACTERISTICS: Dual-Supply (continued) At TA = +25°C, VREF = +5V, AVDD = +16.5V, AVSS = –16.5V, and gain = 6, unless otherwise noted.
DAC8728 SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS: Dual-Supply (continued) At TA = +25°C, VREF = +5V, AVDD = +16.5V, AVSS = –16.5V, and gain = 6, unless otherwise noted.
DAC8728 www.ti.com SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 TYPICAL CHARACTERISTICS: Dual-Supply (continued) At TA = +25°C, VREF = +5V, AVDD = +16.5V, AVSS = –16.5V, and gain = 6, unless otherwise noted. IOVDD SUPPLY CURRENT vs LOGIC INPUT VOLTAGE 3.0 2000 Code = 8000h 1800 IOVDD Supply Current (mA) Output Voltage Noise Density (nV/ÖHz) OUTPUT NOISE SPECTRAL DENSITY vs FREQUENCY 1600 1400 1200 Gain = 6 1000 800 Gain = 4 600 400 IOVDD Values are Shown for Logic Level Change on D0 to D15.
DAC8728 SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS: Single-Supply At TA = +25°C, VREF = +5V, AVDD = +32V, and gain = 6, unless otherwise noted. LINEARITY ERROR vs DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 4 1.00 TA = +25°C 3 0.50 DNL Error (LSB) INL Error (LSB) 2 1 0 -1 DAC0 DAC1 DAC2 DAC3 -2 -3 -4 0 8192 DAC4 DAC5 DAC6 DAC7 0.25 0 -0.25 DAC0 DAC1 DAC2 DAC3 -0.50 -0.75 -1.
DAC8728 www.ti.com SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 TYPICAL CHARACTERISTICS: Single-Supply (continued) At TA = +25°C, VREF = +5V, AVDD = +32V, and gain = 6, unless otherwise noted. LINEARITY ERROR vs DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 4 1.00 TA = -40°C 3 0.50 DNL Error (LSB) INL Error (LSB) 2 1 0 -1 0 -0.25 -0.50 -3 -0.75 -1.
DAC8728 SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS: Single-Supply (continued) At TA = +25°C, VREF = +5V, AVDD = +32V, and gain = 6, unless otherwise noted. LINEARITY ERROR vs TEMPERATURE 4 1.00 3 0.75 2 1 0 -1 INL Min -2 DNL Max 0.50 INL Max DNL Error (LSB) INL Error (LSB) DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE 0.25 0 -0.25 -0.50 -3 DNL Min -0.75 -4 -1.
DAC8728 www.ti.com SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 TYPICAL CHARACTERISTICS: Single-Supply (continued) At TA = +25°C, VREF = +5V, AVDD = +32V, and gain = 6, unless otherwise noted. GAIN ERROR vs TEMPERATURE 5 DAC0 DAC1 DAC2 DAC3 LSB = 0.457mV 4 3 2 5 DAC4 DAC5 DAC6 DAC7 3 1 0 -1 -2 1 0 -1 -2 -3 -4 -4 DAC0 DAC1 DAC2 DAC3 -5 -55 -35 5 -15 25 45 65 Temperature (°C) 85 105 125 -55 -35 -15 5 25 45 65 Temperature (°C) DAC4 DAC5 DAC6 DAC7 85 Figure 68. Figure 69.
DAC8728 SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS: Single-Supply (continued) At TA = +25°C, VREF = +5V, AVDD = +32V, and gain = 6, unless otherwise noted. ZERO-SCALE ERROR vs AVDD GAIN ERROR vs AVDD 5 5 VREF = 2.048V Code = 0100h Gain = 4 3 3 2 1 0 -1 -2 DAC0 DAC1 DAC2 DAC3 -3 -4 2 1 0 -1 -2 DAC4 DAC5 DAC6 DAC7 DAC0 DAC1 DAC2 DAC3 -3 -4 -5 12 16 20 24 AVDD (V) 28 32 36 8 12 16 20 24 AVDD (V) Figure 75.
DAC8728 www.ti.com SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 TYPICAL CHARACTERISTICS: Single-Supply (continued) At TA = +25°C, VREF = +5V, AVDD = +32V, and gain = 6, unless otherwise noted. QUIESCENT CURRENT vs TEMPERATURE QUIESCENT CURRENT vs DIGITAL INPUT CODE 8 8 7 7 6 6 5 5 IAVDD (mA) IAVDD (mA) Code = 8000h 4 3 4 3 2 2 1 1 0 0 -55 -35 -15 5 25 45 65 Temperature (°C) 85 105 0 125 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Figure 80. Figure 81.
DAC8728 SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS: Single-Supply (continued) At TA = +25°C, VREF = +5V, AVDD = +32V, and gain = 6, unless otherwise noted.
DAC8728 www.ti.com SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 TYPICAL CHARACTERISTICS: Single-Supply (continued) At TA = +25°C, VREF = +5V, AVDD = +32V, and gain = 6, unless otherwise noted. OUTPUT VOLTAGE vs SINK CURRENT CAPABILITY OUTPUT VOLTAGE vs SOURCE CURRENT CAPABILITY 2.5 30.5 2.0 30.0 FFFFh FE00h 29.5 1.5 0800h 0400h 0200h VOUT (V) VOUT (V) FF00h 1.0 FC00h 29.0 F800h 28.5 0.5 28.0 0 Operation Near AGND Rail Operation Near AVDD Rail 0100h 0000h 27.5 -0.
DAC8728 SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.com THEORY OF OPERATION GENERAL DESCRIPTION The DAC8728 contains eight DAC channels and eight output amplifiers in a single package. Each channel consists of a resistor-string DAC followed by an output buffer amplifier. The resistor-string section is simply a string of resistors, each with a value of R, from REF to AGND, as shown in Figure 95. This type of architecture provides DAC monotonicity.
DAC8728 www.ti.com SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 USER-CALIBRATION FOR ZERO ERROR AND GAIN ERROR The DAC8728 implements a digital user-calibration function that allows for trimming gain and zero errors on the entire signal chain. This function can eliminate the need for external adjustment circuits. Each DAC channel has a Zero Register and Gain Register.
DAC8728 SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.com If the user-calibration function is not needed, the correction engine can be turned off to speed up the device. Setting the SCE bit in the Configuration Register to '0' turns off the correction engine. Setting SCE to '1' enables the correction engine. When SCE = '0' (default), the data are directly transferred to the DAC Data Register.
DAC8728 www.ti.com SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 INPUT DATA FORMAT The USB/BTC pin defines the input data format and the Offset DAC format. When this pin connects to DGND, the Input DAC data and Offset DAC data are straight binary, as shown in Table 2 and Table 4. When this pin is connected to IOVDD, the Input DAC data and Offset DAC data are twos complement, as shown in Table 3 and Table 5. Table 2.
DAC8728 SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.com OFFSET DACS There are two 16-bit Offset DACs: one for Group A, and one for Group B. The Offset DACs allow the entire output curve of the associated DAC groups to be shifted by introducing a programmable offset. This offset allows for asymmetric bipolar operation of the DACs or unipolar operation with bipolar supplies.
DAC8728 www.ti.com SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 VOUT = GAIN x V1 - (GAIN - 1) x VOFF DAC Channel V1 VOUT AGND-x Offset DAC VOFF OFFSET Figure 96. Output Amplifier and Offset DAC OUTPUT AMPLIFIERS The output amplifiers can swing to 0.5V below the positive supply and 0.5V above the negative supply. This condition limits how much the output can be offset for a given reference voltage. The maximum range of the output for ±17V power and a +5.5V reference is –16.5V to +16.5V for gain = 6.
DAC8728 SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.com GENERAL-PURPOSE INPUT/OUTPUT PIN (GPIO) The GPIO pin is a general-purpose, bidirectional, digital input/output, as shown in Figure 97. When the GPIO pin acts as an output, the pin status is determined by the corresponding GPIO bit in the GPIO Register. The pin output is high-impedance when the GPIO bit is set to '1', and is logic low when the GPIO bit is cleared to '0'.
DAC8728 www.ti.com SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 POWER-ON RESET The DAC8728 contains a power-on reset circuit that controls the output during power-on and power down. This feature is useful in applications where the known state of the DAC output during power-on is important. The Offset DAC Registers, DAC Data Registers, and DAC latches are loaded with the value defined by the RSTSEL pin, as shown in Table 8. The Gain Registers and Zero Registers are loaded with default values.
DAC8728 SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.com UPDATING THE DAC OUTPUTS Depending on the status of both CS and LDAC, and after data have been transferred into the DAC Data registers, the DAC outputs can be updated either in asynchronous mode or synchronous mode. This update mode is established at power-on. If asynchronous mode is desired, the LDAC pin must be permanently tied low before power is applied to the device.
DAC8728 www.ti.com SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 MONITOR OUTPUT PIN (VMON) The VMON pin is the channel monitor output. It monitors either of the DAC outputs, offset DAC outputs, or reference buffer outputs. The channel monitor function consists of an analog multiplexer addressed via the parallel interface, allowing any channel output, reference buffer output, or offset DAC output to be routed to the VMON pin for monitoring using an external ADC.
DAC8728 SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.com PARALLEL INTERFACE The DAC8728 interfaces with microprocessors using a 16-bit data bus. The interface is double-buffered, allowing simultaneous updating of all DACs. Each DAC has an input data register, DAC data register, user-calibration gain register, user-calibration zero register, and DAC latch.
DAC8728 www.ti.com SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 INTERNAL REGISTERS The DAC8728 internal registers consist of the Configuration Register, the Monitor Register, the DAC Input Data Registers, the Zero Registers, the Gain Registers, the DAC Data Registers, and the Busy Flag Register, and are described in the following section. The Configuration Register specifies which actions are performed by the device. Table 11 shows the details. Table 11.
DAC8728 SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.com Monitor Register (default = 0000h). The Monitor Register selects one of the DAC outputs, reference buffer outputs, or offset DAC outputs to be monitored through the VMON pin. Only one bit at a time can be set to '1'. When bits [D15:D4] = '0', the monitor is disabled and VMON is in a Hi-Z state.
DAC8728 www.ti.com SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 Zero Register n (where n = 0 to 7). Default = 0000h. The Zero Register stores the user-calibration data that are used to eliminate the offset error, as shown in Table 14. The data are 16 bits wide, 1 LSB/step, and the total adjustment is –32768 LSB to +32767 LSB, or ±50% of full-scale range. The Zero Register uses a twos complement data format. Table 14.
DAC8728 SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.com GPIO Register. Default = 8000h. The GPIO Register determines the status of the GPIO pin. D15 GPIO (1) D14 X (1) D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X X X X X X X X = don't care. Writing to this bit has no effect; reading the bit returns '0'. GPIO For write operations, the GPIO pin operates as an output.
DAC8728 www.ti.com SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 APPLICATION INFORMATION PRECISION VOLTAGE REFERENCE SELECTION To achieve the optimum performance from the DAC8728 over the full operating temperature range, a precision voltage reference must be used. Careful consideration should be given to the selection of a precision voltage reference. The DAC8728 has two reference inputs, REF-A and REF-B.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DAC8728SPAGR TQFP PAG 64 1500 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2 DAC8728SRTQR QFN RTQ 56 2000 330.0 16.4 8.3 8.3 2.25 12.0 16.0 Q2 DAC8728SRTQT QFN RTQ 56 250 330.0 16.4 8.3 8.3 2.25 12.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC8728SPAGR TQFP PAG 64 1500 367.0 367.0 45.0 DAC8728SRTQR QFN RTQ 56 2000 336.6 336.6 28.6 DAC8728SRTQT QFN RTQ 56 250 336.6 336.6 28.
MECHANICAL DATA MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996 PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 48 0,08 M 33 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 1,05 0,95 0°– 7° 0,75 0,45 Seating Plane 0,08 1,20 MAX 4040282 / C 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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