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DAC8805

FEATURES DESCRIPTION

APPLICATIONS

I A

OUT

AGNDA

R A

DACA

I B

OUT

AGNDB

DACB

DACA

DACB

DGND

D13

LDAC

RSTSEL

R A

COM

V A

REF

R A

OFS

R A

OFS

R B

OFS

R B

OFS

V B

REF

R B

COM

R B

InputA

Parallel

Bus

Interface

Control

Logic

InputB

R A

Power-On

Reset

DAC8805

SBAS391A – DECEMBER 2006 – REVISED MAY 2007

14-Bit, Dual, Parallel Input, Multiplying

Digital-to-Analog Converter

• ± 0.5LSB DNL

The DAC8805 dual, multiplying digital-to-analog

converter (DAC) is designed to operate from a single

• ± 0.5LSB INL

2.7V to 5.5V supply.

• Low Noise: 12nV/ √ Hz

The applied external reference input voltage V

REF

• Low Power: I

= 1 µ A per channel at 2.7V

determines the full-scale output current. An internal

• 2mA Full-Scale Current, with V

REF

= 10V

feedback resistor (R

) provides temperature

• Settling Time: 0.5 µ s

tracking for the full-scale output when combined with

an external, current-to-voltage (I/V) precision

• 14-Bit Monotonic

amplifier.

• 4-Quadrant Multiplying Reference Inputs

A RSTSEL pin allows system reset assertion ( RS) to

• Reference Bandwidth: 10MHz

force all registers to zero code when RSTSEL = '0',

• Reference Input: ± 18V

or to mid-scale code when RSTSEL = '1'.

• Reference Dynamics: –105 THD

Additionally, an internal power-on reset forces all

registers to zero or mid-scale code at power-up,

• Midscale or Zero Scale Reset

depending on the state of the RSTSEL pin.

• Analog Power Supply: +2.7V to +5.5V

A parallel interface offers high-speed

• TSSOP-38 Package

communications. The DAC8805 is packaged in a

• Industry-Standard Pin Configuration

space-saving TSSOP-38 package and has an

• Pin Compatible with the 16-Bit DAC8822

industry-standard pinout. The device is specified

from –40 ° C to +125 ° C.

• Temperature Range: –40 ° C to +125 ° C

For a 16-bit, pin-compatible version, see the

DAC8822 .

• Automatic Test Equipment

• Instrumentation

• Digitally Controlled Calibration

• Industrial Control PLCs

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (24 pages)

PAGE 1
DA C8 80 5 DAC8805 SBAS391A – DECEMBER 2006 – REVISED MAY 2007 14-Bit, Dual, Parallel Input, Multiplying Digital-to-Analog Converter FEATURES • • • • • • • • • • • • • • • • • DESCRIPTION ±0.5LSB DNL ±0.5LSB INL Low Noise: 12nV/√Hz Low Power: IDD = 1µA per channel at 2.7V 2mA Full-Scale Current, with VREF = 10V Settling Time: 0.
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DAC8805 www.ti.com SBAS391A – DECEMBER 2006 – REVISED MAY 2007 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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DAC8805 www.ti.com SBAS391A – DECEMBER 2006 – REVISED MAY 2007 ELECTRICAL CHARACTERISTICS All specifications at TA = –40°C to +125°C, VDD = +2.7V to +5.5V, IOUT = virtual GND, GND = 0V, and VREF = 10V, unless otherwise noted. DAC8805 PARAMETER CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE Resolution Relative accuracy Differential nonlinearity 14 Bits INL ±0.5 ±1 LSB DNL ±0.
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DAC8805 www.ti.
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DAC8805 www.ti.com SBAS391A – DECEMBER 2006 – REVISED MAY 2007 PIN ASSIGNMENTS (continued) Table 1. TERMINAL FUNCTIONS PIN # NAME DESCRIPTION 1, 2 NC No connection 3 ROFSA Bipolar Offset Resistor A. Accepts up to ±18V. In 2-quadrant mode, ROFSA ties to RFBA. In 4-quadrant mode, ROFSA ties to R1A and the external reference. 4 RFBA Internal Matching Feedback Resistor A. Connects to the external op amp for I-V conversion. 5 R1A 4-Quadrant Resistor.
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DAC8805 www.ti.com SBAS391A – DECEMBER 2006 – REVISED MAY 2007 TIMING AND FUNCTIONAL INFORMATION tWR WR A0/1 tAS tAH DATA tDS tDH tLWD LDAC tLDAC tRST RS Figure 1.
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DAC8805 www.ti.com SBAS391A – DECEMBER 2006 – REVISED MAY 2007 Table 2. Address Decoder Pins A1 A0 0 0 OUTPUT UPDATE DAC A 0 1 None 1 0 DAC A and DAC B 1 1 DAC B Table 3. Function of Control Inputs CONTROL INPUTS RS WR LDAC REGISTER OPERATION 0 X X Asynchronous operation. Reset the input and DAC register to '0' when the RSTSEL pin is tied to DGND, and to midscale when RSTSEL is tied to VDD. 1 0 0 Load the input register with all 14 data bits.
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DAC8805 www.ti.com SBAS391A – DECEMBER 2006 – REVISED MAY 2007 TYPICAL CHARACTERISTICS: VDD = +5V Channel A LINEARITY ERROR vs DIGITAL INPUT CODE 1.0 1.0 TA = +25°C 0.8 0.6 0.6 0.4 0.4 0.2 0 -0.2 0 -0.2 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 0 1.0 2048 4096 6144 8192 10240 12288 14336 16383 Code 0 2048 6144 8192 10240 12288 14336 16383 Code Figure 3. LINEARITY ERROR vs DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1.0 TA = -40°C 0.8 0.6 0.4 0.4 DNL (LSB) 0.6 0.
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DAC8805 www.ti.com SBAS391A – DECEMBER 2006 – REVISED MAY 2007 TYPICAL CHARACTERISTICS: VDD = +5V (continued) Channel B LINEARITY ERROR vs DIGITAL INPUT CODE 1.0 1.0 TA = +25°C 0.8 0.6 0.6 0.4 0.4 0.2 0 -0.2 0 -0.2 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 0 1.0 2048 4096 6144 8192 10240 12288 14336 16383 Code 0 2048 4096 6144 8192 10240 12288 14336 16383 Code Figure 8. Figure 9. LINEARITY ERROR vs DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1.0 TA = -40 °C 0.
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DAC8805 www.ti.com SBAS391A – DECEMBER 2006 – REVISED MAY 2007 TYPICAL CHARACTERISTICS: VDD = +5V (continued) MIDSCALE DAC GLITCH MIDSCALE DAC GLITCH VREF = +10V Output Voltage (50mV/div) Output Voltage (50mV/div) VREF = +10V Code: 1FFFh to 2000h Time (0.2ms/div) Time (0.2ms/div) Figure 14. Figure 15.
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DAC8805 www.ti.com SBAS391A – DECEMBER 2006 – REVISED MAY 2007 TYPICAL CHARACTERISTICS: VDD = +2.7V Channel A LINEARITY ERROR vs DIGITAL INPUT CODE 1.0 1.0 TA = +25°C 0.8 0.6 0.6 0.4 0.4 0.2 0 -0.2 0 -0.2 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 0 1.0 2048 4096 6144 8192 10240 12288 14336 16383 Code 0 2048 4096 6144 8192 10240 12288 14336 16383 Code Figure 18. Figure 19. LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR vs DIGITAL INPUT CODE 1.0 TA = -40°C 0.8 TA = -40°C 0.8 0.6 0.
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DAC8805 www.ti.com SBAS391A – DECEMBER 2006 – REVISED MAY 2007 TYPICAL CHARACTERISTICS: VDD = +2.7V (continued) Channel B LINEARITY ERROR vs DIGITAL INPUT CODE 1.0 1.0 TA = +25°C 0.8 0.6 0.6 0.4 0.4 0.2 0 -0.2 0 -0.2 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 0 1.0 2048 4096 6144 8192 10240 12288 14336 16383 Code 0 2048 6144 8192 10240 12288 14336 16383 Code Figure 25. LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR vs DIGITAL INPUT CODE 1.0 TA = -40°C 0.8 0.6 0.4 0.4 DNL (LSB) 0.
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DAC8805 www.ti.com SBAS391A – DECEMBER 2006 – REVISED MAY 2007 TYPICAL CHARACTERISTICS: VDD = +2.7V (continued) DAC GLITCH DAC GLITCH VREF = +10V Output Voltage (50mV/div) Output Voltage (50mV/div) VREF = +10V Code: 1FFFh to 2000h Time (0.2ms/div) Time (0.2ms/div) Figure 30. Figure 31.
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DAC8805 www.ti.com SBAS391A – DECEMBER 2006 – REVISED MAY 2007 TYPICAL CHARACTERISTICS: VDD = +2.7V and +5V SUPPLY CURRENT vs LOGIC INPUT VOLTAGE REFERENCE MULTIPLYING BANDWIDTH UNIPOLAR MODE 180 VDD = +5.0V 140 Attenuation (dB) Supply Current, IDD (mA) 160 120 100 80 60 40 VDD = +2.7V 20 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 6 0 -6 -12 -18 -24 -30 -36 -42 -48 -54 -60 -66 -72 -78 -84 -90 -96 -102 -108 -114 5.
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DAC8805 www.ti.com SBAS391A – DECEMBER 2006 – REVISED MAY 2007 THEORY OF OPERATION The DAC8805 is a multiplying, dual-channel, current output, 14-bit DAC. The architecture, illustrated in Figure 40, is an R-2R ladder configuration with the three MSBs segmented. Each 2R leg of the ladder is either switched to GND or to the IOUT terminal. The IOUT terminal of the DAC is held at a virtual GND potential by the use of an external I/V converter op amp.
PAGE 16
DAC8805 www.ti.com SBAS391A – DECEMBER 2006 – REVISED MAY 2007 APPLICATION INFORMATION DIGITAL INTERFACE The parallel bus interface of the DAC8805 is comprised of a 14-bit data bus, D0—D13, address lines A0 and A1, and a WR control signal. Timing and control functionality are shown in Figure 1, and described in Table 2 and Table 3. The address lines must be set up and stable before the WR signal goes low, to prevent loading improper data to an undesired input register.
PAGE 17
DAC8805 www.ti.com SBAS391A – DECEMBER 2006 – REVISED MAY 2007 APPLICATION INFORMATION (continued) BIPOLAR OUTPUT CIRCUIT The DAC8805, as a 4-quadrant multiplying DAC, can be used to generate a bipolar output. The polarity of the full-scale output (IOUT) is the inverse of the input reference voltage at VREF. Using a dual op amp, such as the OPA2277, full 4-quadrant operation can be achieved with minimal components. Figure 43 demonstrates a ±10VOUT circuit with a fixed +10V reference.
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DAC8805 www.ti.com SBAS391A – DECEMBER 2006 – REVISED MAY 2007 APPLICATION INFORMATION (continued) PROGRAMMABLE CURRENT SOURCE CIRCUIT The DAC8805 can be integrated into the circuit in Figure 44 to implement an improved Howland current pump for precise V/I conversions. Bidirectional current flow and high-voltage compliance are two features of the circuit.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device DAC8805QDBTR Package Package Pins Type Drawing TSSOP DBT 38 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.2 1.8 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC8805QDBTR TSSOP DBT 38 2000 367.0 367.0 38.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.