Datasheet

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DAC9881

FEATURES DESCRIPTION

APPLICATIONS

(1)

Control

Logic

DGND IOV

AGND AV

V -S

REFH

V -F

REFH

RST

RSTSEL

USB/BTC

GAIN

SDI

SCLK

SPIInterface

ShiftRegister

Input

DAC

Latch

LDAC

V -S

REFL

V -F

REFL

Resistor

Network

DAC

NOTE:(1) R =5k forgain=1,W

R =10k forgain=2.W

DAC9881

SerialOut

Control

SDOSEL

SDO

Power-On

Reset

PDN

OUT

DAC9881

www.ti.com

......................................................................................................................................................... SBAS438A – MAY 2008 – REVISED AUGUST 2008

18-Bit, Single-Channel, Low-Noise, Voltage-Output

DIGITAL-TO-ANALOG CONVERTER

234

• 18-Bit Monotonic Over Temperature Range

The DAC9881 is an 18-bit, single-channel,

voltage-output digital-to-analog converter (DAC). It

• Relative Accuracy: ± 2LSB Max

features 18-bit monotonicity, excellent linearity, very

• Low-Noise: 24nV/ √ Hz

low-noise, and fast settling time. The on-chip

• Fast Settling: 5 µ s

precision output amplifier allows rail-to-rail output

• On-Chip Output Buffer Amplifier with swing to be achieved over the full supply range of

2.7V to 5.5V.

Rail-to-Rail Operation

• Single Power Supply: +2.7V to +5.5V

The device supports a standard SPI serial interface

capable of operating with input data clock frequencies

• DAC Loading Control

up to 50MHz. The DAC9881 requires an external

• Selectable Power-On Reset to Zero-Scale or

reference voltage to set the output range of the DAC

Midscale

channel. A programmable power-on reset circuit is

• Power-Down Mode

also incorporated into the device to ensure that the

DAC output powers up at zero-scale or midscale, and

• Unipolar Straight Binary or

remains there until a valid write command.

Twos Complement Input Mode

Additionally, the DAC9881 has the capability to

• Fast SPI™ Interface with Schmitt-Triggered

function in either unipolar straight binary or twos

Inputs: up to 50MHz, 1.8V/3V/5V Logic

complement mode. The DAC9881 provides

• Small Package: QFN-24, 4mm × 4mm

low-power operation. To further save energy,

power-down mode can be achieved by accessing the

PDN pin, thereby reducing the current consumption to

• Automatic Test Equipment

25 µ A at 5V. Power consumption is 4mW at 5V,

reducing to 125 µ W in power-down mode.

• Precision Instrumentation

• Industrial Control

The DAC9881 is available in a 4mm × 4mm QFN-24

• Data Acquisition Systems

package with a specified temperature range of – 40 ° C

to +105 ° C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 SPI, QSPI are trademarks of Motorola, Inc.

3 MICROWIRE is a trademark of National Semiconductor.

4 All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (39 pages)

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DA DAC9881 C9 88 1 www.ti.com .........................................................................................................................................................
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DAC9881 SBAS438A – MAY 2008 – REVISED AUGUST 2008 ......................................................................................................................................................... www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
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DAC9881 www.ti.com ......................................................................................................................................................... SBAS438A – MAY 2008 – REVISED AUGUST 2008 ELECTRICAL CHARACTERISTICS: AVDD = 5V All specifications at TA = TMIN to TMAX, AVDD = +4.75V to +5.5V, IOVDD = +1.8V to +5.5V, VREFH = 5V, VREFL = 0V, and gain = 1X mode, unless otherwise noted.
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DAC9881 SBAS438A – MAY 2008 – REVISED AUGUST 2008 ......................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS: AVDD = 5V (continued) All specifications at TA = TMIN to TMAX, AVDD = +4.75V to +5.5V, IOVDD = +1.8V to +5.5V, VREFH = 5V, VREFL = 0V, and gain = 1X mode, unless otherwise noted.
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DAC9881 www.ti.com ......................................................................................................................................................... SBAS438A – MAY 2008 – REVISED AUGUST 2008 ELECTRICAL CHARACTERISTICS: AVDD = 2.7V All specifications at TA = TMIN to TMAX, AVDD = +2.7V to +3.3V, IOVDD = +1.8V to AVDD, VREFH = 2.5V, VREFL = 0V and gain = 1X mode, unless otherwise noted. DAC9881 PARAMETER CONDITIONS MIN TYP MAX UNIT ±2.5 ±3.
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DAC9881 SBAS438A – MAY 2008 – REVISED AUGUST 2008 ......................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS: AVDD = 2.7V (continued) All specifications at TA = TMIN to TMAX, AVDD = +2.7V to +3.3V, IOVDD = +1.8V to AVDD, VREFH = 2.5V, VREFL = 0V and gain = 1X mode, unless otherwise noted.
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DAC9881 www.ti.com .........................................................................................................................................................
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DAC9881 SBAS438A – MAY 2008 – REVISED AUGUST 2008 ......................................................................................................................................................... www.ti.com TIMING DIAGRAMS Case 1: Standalone operation without SDO, LDAC tied low. t1 t2 CS t3 t4 t7 t6 t5 Input Register and DAC Latch Updated SCLK t8 Bit 23 (N) SDI LDAC t9 Bit 22 (N) Bit 1 (N) Bit 0 (N) Low Case 2: Standalone operation without SDO, LDAC active.
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DAC9881 www.ti.com ......................................................................................................................................................... SBAS438A – MAY 2008 – REVISED AUGUST 2008 TIMING CHARACTERISTICS for Figure 1 (1) (2) (3) At –40°C to +105°C, unless otherwise noted. PARAMETER fSCLK Maximum clock frequency t1 Minumum CS high time MAX UNIT 2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD CONDITIONS MIN 40 MHz 3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD 50 MHz 2.
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DAC9881 SBAS438A – MAY 2008 – REVISED AUGUST 2008 ......................................................................................................................................................... www.ti.com Case 1: Standalone operation with output from SDO, LDAC tied low. t1 t2 CS Input Register and DAC Latch Updated t3 t4 t7 t6 t5 SCLK t8 Bit 23 (N) SDI t9 Bit 22 (N) Bit 1 (N) t11 High-Z SDO LDAC Bit 23 (N - 1) from Input Reg. Bit 22 (N - 1) from Input Reg.
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DAC9881 www.ti.com ......................................................................................................................................................... SBAS438A – MAY 2008 – REVISED AUGUST 2008 Case 1: Daisy Chain, LDAC tied low.
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DAC9881 SBAS438A – MAY 2008 – REVISED AUGUST 2008 ......................................................................................................................................................... www.ti.com TIMING CHARACTERISTICS for Figure 2 and Figure 3 (1) (2) (3) At –40°C to +105°C, unless otherwise noted. PARAMETER fSCLK Maximum clock frequency t1 Minumum CS high time MAX UNIT 2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD CONDITIONS MIN 20 MHz 3.6 ≤ AVDD ≤ 5.5V, 2.
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DAC9881 www.ti.com ......................................................................................................................................................... SBAS438A – MAY 2008 – REVISED AUGUST 2008 TYPICAL CHARACTERISTICS: AVDD = +5V At TA = +25°C, VREFH = +5.0V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted. LINEARITY ERROR vs DIGITAL INPUT CODE 2.0 TA = +25°C 1.5 1.5 1.0 1.0 DNL Error (LSB) INL Error (LSB) 2.0 DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 0.
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DAC9881 SBAS438A – MAY 2008 – REVISED AUGUST 2008 ......................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: AVDD = +5V (continued) At TA = +25°C, VREFH = +5.0V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted. LINEARITY ERROR vs TEMPERATURE DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE 2.0 2.0 1.5 1.5 INL Max 1.0 DNL Error (LSB) INL Error (LSB) 1.0 0.5 0 -0.
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DAC9881 www.ti.com ......................................................................................................................................................... SBAS438A – MAY 2008 – REVISED AUGUST 2008 TYPICAL CHARACTERISTICS: AVDD = +5V (continued) At TA = +25°C, VREFH = +5.0V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted. LINEARITY ERROR vs REFERENCE VOLTAGE DIFFERENTIAL LINEARITY ERROR vs REFERENCE VOLTAGE 2.0 2.0 1.5 1.5 INL Max 1.0 DNL Error (LSB) INL Error (LSB) 1.0 0.
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DAC9881 SBAS438A – MAY 2008 – REVISED AUGUST 2008 ......................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: AVDD = +5V (continued) At TA = +25°C, VREFH = +5.0V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted. AVDD SUPPLY CURRENT vs TEMPERATURE AVDD POWER-DOWN CURRENT vs TEMPERATURE 50 AVDD Power-Down Current (mA) AVDD Supply Current (mA) 1200 1000 800 VREFH = 5.
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DAC9881 www.ti.com ......................................................................................................................................................... SBAS438A – MAY 2008 – REVISED AUGUST 2008 TYPICAL CHARACTERISTICS: AVDD = +5V (continued) At TA = +25°C, VREFH = +5.0V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted. OUTPUT VOLTAGE vs DRIVE CURRENT CAPABILITY (Operation Near AGND Rail) IOVDD SUPPLY CURRENT vs LOGIC INPUT VOLTAGE 200 0.
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DAC9881 SBAS438A – MAY 2008 – REVISED AUGUST 2008 ......................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: AVDD = +5V (continued) At TA = +25°C, VREFH = +5.0V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted. LARGE SIGNAL SETTLING TIME (GAIN = 2X MODE) VREFH = 2.5V LARGE SIGNAL SETTLING TIME (GAIN = 2X MODE) VREFH = 2.
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DAC9881 www.ti.com ......................................................................................................................................................... SBAS438A – MAY 2008 – REVISED AUGUST 2008 TYPICAL CHARACTERISTICS: AVDD = +5V (continued) At TA = +25°C, VREFH = +5.0V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted. MAJOR CARRY GLITCH MAJOR CARRY GLITCH Code Change: 1FFFFh to 20000h Output Loaded with 10kW and 50pF to AGND Gain = 1X Mode VREFH = +2.
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DAC9881 SBAS438A – MAY 2008 – REVISED AUGUST 2008 ......................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: AVDD = +2.7V At TA = +25°C, VREFH = +2.5V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted. LINEARITY ERROR vs DIGITAL INPUT CODE 3.0 DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 2.0 TA = +25°C TA = +25°C 1.5 2.0 DNL Error (LSB) INL Error (LSB) 1.
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DAC9881 www.ti.com ......................................................................................................................................................... SBAS438A – MAY 2008 – REVISED AUGUST 2008 TYPICAL CHARACTERISTICS: AVDD = +2.7V (continued) At TA = +25°C, VREFH = +2.5V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted. LINEARITY ERROR vs REFERENCE VOLTAGE DIFFERENTIAL LINEARITY ERROR vs REFERENCE VOLTAGE 4.0 2.0 3.0 1.5 INL Max DNL Max 1.
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DAC9881 SBAS438A – MAY 2008 – REVISED AUGUST 2008 ......................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: AVDD = +2.7V (continued) At TA = +25°C, VREFH = +2.5V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted. OUTPUT VOLTAGE vs DRIVE CURRENT CAPABILITY (Operation Near AVDD Rail) 2.70 OUTPUT VOLTAGE vs DRIVE CURRENT CAPABILITY (Operation Near AGND Rail) 0.
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DAC9881 www.ti.com ......................................................................................................................................................... SBAS438A – MAY 2008 – REVISED AUGUST 2008 TYPICAL CHARACTERISTICS: AVDD = +2.7V (continued) At TA = +25°C, VREFH = +2.5V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted. MAJOR CARRY GLITCH MAJOR CARRY GLITCH Code Change: 1FFFFh to 20000h Output Loaded with 10kW and 50pF to AGND Gain = 1X Mode VREFH = +2.
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DAC9881 SBAS438A – MAY 2008 – REVISED AUGUST 2008 ......................................................................................................................................................... www.ti.com THEORY OF OPERATION GENERAL DESCRIPTION The DAC9881 is a single-channel, 18-bit, serial-input, voltage-output digital-to-analog converter (DAC).
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DAC9881 www.ti.com .........................................................................................................................................................
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DAC9881 SBAS438A – MAY 2008 – REVISED AUGUST 2008 ......................................................................................................................................................... www.ti.com ANALOG OUTPUT The DAC9881 offers a force and sense output configuration for the high open-loop gain output amplifier. This feature allows the loop around the output amplifier to be closed at the load (as shown in Figure 66), thus ensuring an accurate output voltage.
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DAC9881 www.ti.com ......................................................................................................................................................... SBAS438A – MAY 2008 – REVISED AUGUST 2008 REFERENCE INPUTS The reference high input, VREFH, can be set to any voltage in the range of 1.25V to AVDD. The reference low input, VREFL, can be set to any voltage in the range of –0.2V to +0.2V (to provide a small offset to the output of the DAC9881, if desired).
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DAC9881 SBAS438A – MAY 2008 – REVISED AUGUST 2008 ......................................................................................................................................................... www.ti.com OUTPUT RANGE The maximum output range of the DAC9881 is VREFL to (VREFH – VREFL) × G, where G is the output buffer gain set by the GAIN pin. When the GAIN pin is connected to DGND, the output buffer gain = 1. When the GAIN pin is connected to IOVDD, the output buffer gain = 2.
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DAC9881 www.ti.com ......................................................................................................................................................... SBAS438A – MAY 2008 – REVISED AUGUST 2008 POWER-ON RESET The DAC9881 has a power-on reset function. After power-on, the value of the input register, the DAC latch, and the output from the VOUT pin are set to the value defined by the RSTSEL pin.
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DAC9881 SBAS438A – MAY 2008 – REVISED AUGUST 2008 ......................................................................................................................................................... www.ti.com In Daisy-Chain mode, SCLK is continuously applied to the input shift register while CS is low. If more than 24 clock pulses are applied, the data ripple out of the shift register and appear on the SDO line. These data are clocked out on the falling edge of SCLK and are valid on the rising edge.
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DAC9881 www.ti.com ......................................................................................................................................................... SBAS438A – MAY 2008 – REVISED AUGUST 2008 APPLICATION INFORMATION BIPOLAR OPERATION USING THE DAC9881 The DAC9881 is designed for single-supply operation; however, a bipolar output is also possible using the circuit shown in Figure 70. This circuit gives a bipolar output voltage of VBIP.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com (3) 11-Apr-2013 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing DAC9881SBRGER VQFN RGE 24 DAC9881SBRGET VQFN RGE DAC9881SRGER VQFN RGE DAC9881SRGET VQFN RGE SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3000 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 24 250 180.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 24 3000 330.0 12.4 4.3 4.3 1.5 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC9881SBRGER VQFN RGE 24 3000 338.1 338.1 20.6 DAC9881SBRGET VQFN RGE 24 250 210.0 185.0 35.0 DAC9881SRGER VQFN RGE 24 3000 338.1 338.1 20.6 DAC9881SRGET VQFN RGE 24 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.