Datasheet

DOUBLE-BUFFERED INTERFACE
Load DAC Pin ( LDAC)
1.8V TO 5V LOGIC INTERFACE
POWER-SUPPLY SEQUENCE
DAC9881
SBAS438A – MAY 2008 – REVISED AUGUST 2008 ......................................................................................................................................................... www.ti.com
In Daisy-Chain mode, SCLK is continuously applied to the input shift register while CS is low. If more than 24
clock pulses are applied, the data ripple out of the shift register and appear on the SDO line. These data are
clocked out on the falling edge of SCLK and are valid on the rising edge. By connecting this line to the SDI input
on the next DAC in the chain, a multi-DAC interface is constructed. 24 clock pulses are required for each DAC in
the chain. Therefore, the total number of clock cycles must be equal to (24 x N), where N is the total number of
devices in the chain. When the serial transfer to all devices is complete, CS should be taken high. This action
prevents any further data from being clocked into the input shift register. The contents in the shift registers are
transferred into the relevant input registers on the rising edge of the CS signal.
A continuous SCLK source may be used if CS can be held low for the correct number of clock cycles.
Alternatively, a burst clock containing the exact number of clock cycles can be used and CS can be taken high
some time later. When the transfer to all input registers is complete, a common LDAC signal updates all DAC
registers, and all analog outputs update simultaneously.
The DAC9881 has a double-buffered interface consisting of two register banks: the input register and the DAC
latch. The input register is connected directly to the input shift register and the digital code is transferred to the
input register upon completion of a valid write sequence. The DAC latch contains the digital code used by the
resistor R-2R ladder. The contents of the DAC latch defines the output from the DAC.
Access to the DAC latch is controlled by the LDAC pin. When LDAC is high, the DAC latch is latched and the
input register can change state without affecting the contents of the DAC latch. When LDAC is low, however, the
DAC latch becomes transparent and the contents of the input register is transferred to the DAC register.
LDAC transfers data from the input register to the DAC latch (and, therefore, updates the DAC output). The
contents of the DAC latch (and the output from DAC) can be changed in two ways, depending on the status of
LDAC.
Synchronous Mode
When LDAC is tied low, the DAC latch updates as soon as new data are transferred into the input register after
the rising edge of CS.
Asynchronous Mode
When LDAC is high, the DAC latch is latched. The DAC latch (and DAC output) is not updated at the same time
that the input register is written to. When LDAC goes low, the DAC latch updates with the contents of the input
register.
All digital input and output pins are compatible with any logic supply voltage between 1.8V and 5V. Connect the
interface logic supply voltage to the IOV
DD
pin. Although timing is specified down to 2.7V (see the Timing
Characteristics ), IOV
DD
can operate as low as 1.8V, but with degraded timing and temperature performance. For
the lowest power consumption, logic V
IH
levels should be as close as possible to IOV
DD
, and logic V
IL
levels
should be as close as possible to GND.
For the device to work properly, IOVDD must not come up before AV
DD
, and the reference voltage must come up
after the AV
DD
supply. Additionally, because the DAC input shift register is not reset during a power-on reset or
hardware reset, the CS pin must not be unintentionally asserted during power-up of the device. To avoid
improper power-up, it is recommended that the CS and LDAC pins be connected to IOV
DD
through pull-up
resistors. To ensure that the electrostatic discharge (ESD) protection circuitry of this device is not activated, all
other digital pins must be held at ground potential until IOV
DD
is applied.
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Product Folder Link(s): DAC9881