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DCP02

FEATURES DESCRIPTION

APPLICATIONS

BIAS

Power

Stage

OUT

Divide-by-2

Reset

800kHz

Oscillator

Watchdog/

Startup

PSU

Thermal

Shutdown

SYNC/DISABLE

PowerControllerIC

DCP02 Series

SBVS011K – MARCH 2000 – REVISED FEBRUARY 2008

www.ti.com

Miniature, 2W, Isolated

UNREGULATED DC/DC CONVERTERS

• Up To 89% Efficiency

The DCP02 series is a family of 2W, isolated,

unregulated DC/DC converters. Requiring a minimum

• Thermal Protection

of external components and including on-chip device

• Device-to-Device Synchronization

protection, the DCP02 series provides extra features

• SO-28 Power Density of 106W/in

(6.5W/cm

)

such as output disable and synchronization of

• EN55022 Class B EMC Performance switching frequencies.

• UL1950 Recognized Component

The use of a highly integrated package design results

in highly reliable products with power densities of

• JEDEC 14-Pin and SO-28 Packages

79W/in

(4.8W/cm

) for DIP-14, and 106W/in

(6.5W/cm

) for SO-28. This combination of features

and small size makes the DCP02 suitable for a wide

• Point-of-Use Power Conversion

range of applications.

• Ground Loop Elimination

• Data Acquisition

• Industrial Control and Instrumentation

• Test Equipment

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (17 pages)

PAGE 1
DCP02 Series DC P0 2 DC P0 2 www.ti.com SBVS011K – MARCH 2000 – REVISED FEBRUARY 2008 Miniature, 2W, Isolated UNREGULATED DC/DC CONVERTERS FEATURES DESCRIPTION 1 • • • • • • • 2 Up To 89% Efficiency Thermal Protection Device-to-Device Synchronization SO-28 Power Density of 106W/in3 (6.
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DCP02 Series www.ti.com SBVS011K – MARCH 2000 – REVISED FEBRUARY 2008 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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DCP02 Series www.ti.com SBVS011K – MARCH 2000 – REVISED FEBRUARY 2008 ELECTRICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SWITCHING/SYNCHRONIZATION Oscillator frequency (fOSC) Switching frequency = fOSC/2 800 Sync input low 0 Sync input current kHz 0.
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DCP02 Series www.ti.com SBVS011K – MARCH 2000 – REVISED FEBRUARY 2008 DEVICE INFORMATION NVA PACKAGE DIP-14 (Single-DIP) (Top View) VS 1 0V 2 NVA PACKAGE DIP-14 (Dual-DIP) (Top View) 14 SYNC VS 1 0V 2 14 SYNC DCP02 DCP02 0V 5 0V 5 +VOUT 6 +VOUT 6 NC 7 -VOUT 7 8 NC Table 1. Pin Description (Single-DIP) NC Table 3. TERMINAL FUNCTIONS (Dual-DIP) TERMINAL NAME 8 TERMINAL NO. DESCRIPTION NAME NO.
PAGE 5
DCP02 Series www.ti.com SBVS011K – MARCH 2000 – REVISED FEBRUARY 2008 TYPICAL CHARACTERISTICS At TA = +25°C, unless otherwise noted. DCP020505P VOUT vs TEMPERATURE (75% Load) 60 5.04 50 5.02 40 5.00 30 VOUT (V) Emission Level, Peak (dBmA) DCP020505P CONDUCTED EMISSIONS (500mA Load) 20 4.96 10 4.94 0 4.92 -10 4.90 -20 0.15 1 5.4 10 -40 30 0 20 40 60 80 100 Temperature (°C) Figure 1. Figure 2. DCP021205P VOUT vs LOAD DCP021205P POWER OUT vs TEMPERATURE (400mA Load) 2.5 5.
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DCP02 Series www.ti.com SBVS011K – MARCH 2000 – REVISED FEBRUARY 2008 FUNCTIONAL DESCRIPTION OVERVIEW This interference occurs because of the small variations in switching frequencies between the DC/DC converters. The DCP02 offers up to 2W of unregulated output power from a 5V, 12V, 15V, or 24V input source with a typical efficiency of up to 89%. This efficiency is achieved through highly integrated packaging technology and the implementation of a custom power stage and control IC.
PAGE 7
DCP02 Series www.ti.com SBVS011K – MARCH 2000 – REVISED FEBRUARY 2008 ADDITIONAL FUNCTIONS DISABLE/ENABLE The DCP02 can be disabled or enabled by driving the SYNC pin using an open drain CMOS gate. If the SYNC pin is pulled low, the DCP02 will be disabled. The disable time depends upon the external loading; the internal disable function is implemented in 2µs. Removal of the pull down causes the DCP02 to be enabled.
PAGE 8
DCP02 Series www.ti.com SBVS011K – MARCH 2000 – REVISED FEBRUARY 2008 APPLICATION INFORMATION The DCP01B, DCV01, and DCP02 are three families of miniature DC/DC converters providing an isolated unregulated voltage output. All are fabricated using a CMOS/DMOS process with the DCP01B replacing the familiar DCP01 family that was fabricated from a bipolar process. The DCP02 is essentially an extension of the DCP01B family, providing a higher power output with a significantly improved load regulation.
PAGE 9
DCP02 Series www.ti.com SBVS011K – MARCH 2000 – REVISED FEBRUARY 2008 Decoupling Ceramic Capacitors Input Capacitor and the Effects of ESR All capacitors have losses because of internal equivalent series resistance (ESR), and to a lesser degree, equivalent series inductance (ESL). Values for ESL are not always easy to obtain. However, some manufacturers provide graphs of frequency versus capacitor impedance.
PAGE 10
DCP02 Series www.ti.com SBVS011K – MARCH 2000 – REVISED FEBRUARY 2008 Clearly, increasing the capacitance has a much smaller effect on the output ripple voltage than does reducing the value of the ESR for the filter capacitor. DUAL OUTPUT VOLTAGE DCP AND DCVs The voltage output for the dual DCPs is half wave rectified; therefore, the discharge time is 1.25µs. Repeating the above calculations using the 100% load resistance of 25Ω (0.2A per output), the results are: τ = 25µs tDIS = 1.
PAGE 11
DCP02 Series www.ti.com SBVS011K – MARCH 2000 – REVISED FEBRUARY 2008 Figure 11. Example of PCB Layout, Component-Side View Figure 12.
PAGE 12
DCP02 Series www.ti.
PAGE 13
PACKAGE OPTION ADDENDUM www.ti.
PAGE 14
PACKAGE OPTION ADDENDUM www.ti.
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MECHANICAL DATA MPDS106A – AUGUST 2001 – REVISED NOVEMBER 2001 DVB(R-PDSO-G12/28) –A– 28 PLASTIC SMALL-OUTLINE 18,10 17,70 11,20 10,82 C 0°–8° 15 1,27 0,40 F 7,60 7,40 –B– D 10,65 10,01 0,25 M B M Index Area 1 14 0,30 0,10 2,65 2,35 0,75 0,25 x 45° Base Plane –C– Seating Plane 1,27 G 0,32 0,23 0,51 0,33 0,10 0,25 M C A M B S 4202104/B 11/01 G. Lead width, as measured 0,36 mm or greater above the seating plane, shall not exceed a maximum value of 0,61 mm. H.
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