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20-BIT ANALOG-TO-DIGITAL CONVERTER

DDC101

DESCRIPTION

The DDC101 is a precision, wide dynamic range, charge

digitizing A/D converter with 20-bit resolution. Low

level current output devices, such as photosensors, can be

directly connected to its input. The most stringent accu-

racy requirements of many unipolar output sensor appli-

cations occur at low signal levels. To meet this require-

ment, Burr-Brown developed the adaptive delta modula-

tion architecture of the DDC101 to provide linearly

improving noise and linearity errors as the input signal

level decreases. The DDC101 combines the functions of

current-to-voltage conversion, integration, input program-

mable gain amplification, A/D conversion, and digital

filtering to produce precision, wide dynamic range re-

sults. The input signal can be a low level current con-

nected directly into the unit or a voltage connected

through a user selected resistor. Although the DDC101 is

optimized for unipolar signals, it can also accurately

digitize bipolar input signals. The patented delta modula-

tion topology combines charge integration and digitiza-

tion functions. Oversampling and digital filtering reduce

system noise dramatically. Correlated Double Sampling

(CDS) captures and eliminates steady state and conver-

sion cycle dependent offset and switching errors that are

not eliminated with conventional analog circuits.

The DDC101 block diagram is shown below. During

conversion, the input signal is collected on the internal

integration capacitance for a user determined integration

period. A high precision, autozeroed comparator samples

the analog input node. Tracking logic updates the internal

high resolution D/A converter at a 2MHz rate to maintain

the analog input at virtual ground. A user programmable

digital filter oversamples the tracking logic’s output. The

digital filter passes a low noise, high resolution digital

output to the serial I/O register. The serial outputs of

multiple DDC101 units can be easily connected together

in series or parallel if desired to minimize interconnections.

● MONOLITHIC CHARGE INPUT ADC

● DIGITAL FILTER NOISE REDUCTION:

0.9ppm, rms

● DIGITAL ERROR CORRECTION: CDS

● CONVERSION RATE: Up to 15kHz

● USER FRIENDLY EVALUATION FIXTURE

APPLICATIONS

FEATURES

● DIRECT PHOTOSENSOR DIGITIZATION

● PRECISION INSTRUMENTATION

● INFRARED PYROMETRY

● PRECISION PROCESS CONTROL

● CT SCANNER DAS

● CHEMICAL ANALYZERS

INT

Digital Integration,

Tracking and

Control Logic

Digital Filter and

Error Correction

Serial I/O

Serial In

Serial Out

Reset

DAC

CDAC

DDC101 Integrated Circuit

Comparator

REF

Analog

Input

Ground

Setup

Oversampled

Digital Out

18 Bits

20 Bits

Test In

Test Current

1993 Burr-Brown Corporation PDS-1211E Printed in U.S.A. March, 1998

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111

Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132

DDC101

SBAS029

Summary of content (29 pages)

PAGE 1
® DDC101 101 DDC 20-BIT ANALOG-TO-DIGITAL CONVERTER FEATURES APPLICATIONS ● MONOLITHIC CHARGE INPUT ADC ● DIRECT PHOTOSENSOR DIGITIZATION ● DIGITAL FILTER NOISE REDUCTION: 0.
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TABLE OF CONTENTS The second block diagram, Figure 2, shows the DDC101 circuit architecture which implements these functions monolithically. During each conversion, the input signal current is collected on the internal integration capacitance, CINT, as charge for a user determined integration period, TINT. As the integration capacitor collects input charge, the tracking logic updates the internal high resolution D/A converter at a 2MHz rate to maintain the analog input node at virtual ground.
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An internal test current source is provided for basic functionality testing and diagnostics. This approximately 100nA current source is pin activated and sums with the external input current. Capacitor Digital-to-Analog Converter (CDAC). By switching between ground and VREF the binary weighted capacitor array of the CDAC accumulates the input signal’s charge to keep the comparator input at virtual ground. Figure 3 shows a more detailed circuit configuration of the DDC101.
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SECTION 2 SPECIFICATIONS ELECTRICAL All specifications with unipolar current input range, TINT = 1ms, correlated double sampling enabled, System Clock = 2MHz, VREF = –2.5V, TA = +25°C and VS = ±5VDC, unless otherwise noted.
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SPECIFICATIONS (CONT) ELECTRICAL All specifications with unipolar current input range, TINT = 1ms, correlated double sampling enabled, System Clock = 2MHz, VREF = –2.5V, TA = +25°C and VS = ±5VDC, unless otherwise noted. DDC101 PARAMETER CONDITIONS POWER SUPPLY REQUIREMENTS Operation(5) Quiescent Current, Positive Supply Analog, VS+ Digital, VDD+ Quiescent Current, Negative Supply Operating Power MIN TYP MAX UNITS ±4.75 ±5 15.6 8.9 6.7 18.0 170 ±5.25 19.
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PIN CONFIGURATION Top View 24-Lead SOIC VS–, ANALOG 1 24 REFERENCE BUFFER BYPASS ANALOG COMMON 2 23 VREF ANALOG In 3 22 TEST In ANALOG COMMON 4 21 RESET SETUP In VS+, ANALOG 5 20 SETUP VS+, ANALOG 6 19 READ DATA/SETUP RESET SYSTEM In 7 18 DATA TRANSMIT In FDS (Final Data Point Start) In 8 17 OVERFLOW + Out SYSTEM CLOCK 9 16 OVERFLOW – Out DATA CLOCK 10 15 DATA VALID Out DATA INPUT 11 14 DATA OUTPUT VDD+, DIGITAL 12 13 DIGITAL GROUND SECTION 3 PIN DESCRIPTIONS
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PIN DESCRIPTIONS (CONT) PIN NUMBER NAME 18 DATA TRANSMIT In This input controls the transmission of data from the serial I/O register of the DDC101. It can be activated anytime after DATA VALID out becomes active. It must remain active until all data has been collected from the serial I/O register(s) of all DDC101s in the data path. 19 READ DATA/ SETUP In This input can be used to read back the current SETUP data.
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Continuous Integration Timing TINT' TINT SYSTEM CLOCK t1 FDS In should be coincident with negative clock. t2 FDS In Internal Oversampling Interval FDS initiates oversampling period. End of oversample period initiates reset for next integration. M Clock Periods Internal Reset M Clock Periods Next integration begins when 1 clock period wide Internal Reset ends. DATA VALID Out Non-Continuous Integration Timing SYSTEM CLOCK FDS In should be coincident with negative clock.
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TIMING DIAGRAMS (CONT) SYSTEM CLOCK In t8 t14 DATA VALID Out Read Clear Read Clear OVERFLOW + Out OVERFLOW – Out DATA VALID Out can be used to latch data from the overflow status outputs. FIGURE 7. OVERFLOW Out Monitoring Timing Diagram. SYSTEM CLOCK In t15 t16 SYSTEM CLOCK FIGURE 8. System Clock Timing.
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TYPICAL PERFORMANCE CURVES ELECTRICAL System Clock = 2MHz, VS = ±5VDC, VREF = –2.5V, L = 1 Integration/Conversion, and TA = +25°C, unless otherwise noted.
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TYPICAL PERFORMANCE CURVES (CONT) ELECTRICAL System Clock = 2MHz, VS = ±5VDC, VREF = –2.5V, L = 1 Integration/Conversion, and TA = +25°C, unless otherwise noted. NOISE vs INPUT CAPACITANCE, UNIPOLAR INPUT NOISE vs OVERSAMPLING, UNIPOLAR INPUT 50 40 1ms Integration Time K = 16 Acquisition Clocks CIN = 0pF 1ms Integration Time M = 128 Oversamples 35 Noise (ppm, rms) Noise (ppm, rms) 30 25 No CDS 20 15 10 L = 1 Integration/Conversion 10 L = 128 1.
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TYPICAL PERFORMANCE CURVES (CONT) ELECTRICAL System Clock = 2MHz, VS = ±5VDC, VREF = –2.5V, L = 1 Integration/Conversion, and TA = +25°C, unless otherwise noted.
PAGE 13
SECTION 5 DISCUSSION OF SPECIFICATIONS input range, an input current of 0.5µA integrated for 1ms will result in the full scale charge of 500pC. For voltage inputs, the input resistor is chosen to achieve the proper full scale input current. As an example, for a 5V full scale input, a 10MΩ input resistor is selected to achieve a full scale input current of 0.5µA (1ms integration time). INPUT The DDC101 is a charge digitizing A/D converter.
PAGE 14
maximum input voltage based upon several selections of input current and input resistor for unipolar input range. The accuracy of the input resistor will add directly to the DC Gain Error of the DDC101; the drift of the input resistor will add directly to the Gain Drift of the DDC101. Note that the DDC101 output noise decreases as RIN increases. This is because the DDC101 noise gain decreases and the input resistance current noise decreases as RIN increases.
PAGE 15
NOISE The noise of the DDC101 improves as the input signal level decreases, thus very low level signals can be resolved. Noise is shown in the specification table for low level inputs. For unipolar input range, the DDC101 noise at low level inputs is dominated by comparator noise gained to the output; at full scale inputs, the noise is dominated by D/A converter noise.
PAGE 16
N Aquisition Time, K X Time, Clock Cycles Oversampled Initial Data Point M Tracking Interval Final Data Point Start M X Oversampled Final Data Point Measurement Time Digital Output DDC101 digital output is precise integration of input during measurement time. FIGURE 11. Equivalent Integrator Output for Single Integration. Aquisition Time K M Time, Clock Cycles X Oversampled Initial Data Point Reset of Previous Integration Tracking Interval Digital Output FIGURE 12.
PAGE 17
Correlated Double Sampling is implemented in the DDC101 by subtracting the Initial Data Point from the Final Data Point. Thus, the error correction is updated automatically for each integration. When operating in the unipolar input range, CDS functions with either output data format—straight binary or binary two’s complement. When operating in the bipolar input range, CDS functions with binary two’s complement output data format only.
PAGE 18
IFS TINT 1nA 10nA 100nA 1µA 5µA 7.8µA 500ms 50ms 5ms 500µs 100µs 64µs Conversion Cycle Integration 1 Integration 2 Time TABLE III. Input Current vs Integration Time Examples for Maximum Charge. Unipolar input range maximum charge = 500pC. ±IFS TINT 1nA 10nA 100nA 1µA 2.5µA 7.8µA 250ms 25ms 2.5ms 250µs 100µs 32µs FIGURE 15. Conversion Cycle with Two Integrations. TABLE IV. Input Current vs Integration Time Examples for Maximum Charge. Bipolar input range maximum charge = ±250pC.
PAGE 19
Basic Integration Frequency Response The sin(x)/x basic integration characteristic is controlled by the digital filter’s measurement time (TMEAS). The measurement frequency, fMEAS is l/TMEAS. The input frequency response of the DDC101 is down –3dB at fMEAS/2.26 with a null at fMEAS. Subsequent nulls are at harmonics 2fMEAS, 3fMEAS, 4fMEAS, etc. as shown in the frequency response curve below.
PAGE 20
Gain (dB) 0 0 –5 –5 –10 –10 –15 –15 –20 –20 –25 –25 –30 –30 –35 –35 –40 N = 1000 L = 64 fCONV = 31Hz –40 fOS 10k 1k 100k 1M 1 10 Frequency (Hz) FIGURE 17. Oversampling Frequency Response for M = 256 (fCLK = 2MHz). 1ms 1ms 1ms 1ms 1ms 10ms 10ms 10ms 10ms 10ms 2 8 16 64 256 2 8 16 64 256 CONVERSION –3dB TIME FREQUENCY 2ms 8ms 16ms 64ms 256ms 20ms 80ms 160ms 640ms 2560ms 1k 221Hz 55Hz 27.5Hz 6.9Hz 1.73Hz 22.1Hz 5.5Hz 2.75Hz 0.69Hz 0.
PAGE 21
0 SYSTEM SETUP After power up, the Reset System and FDS signal inputs should be held low (active), while the SETUP register is loaded by the user. After the SETUP register is loaded, the Reset System input should transition to inactive while the FDS input remains active. The FDS should transition to inactive at the start of operation. Thereafter, Reset System should stay inactive and the FDS should be used to control each integration cycle.
PAGE 22
BIPOLAR INPUT RANGE For Binary Two’s Complement, output data format, the output word is a 21-bit Two’s Complement word. The first bit is the sign bit followed by the Most Significant Bit (MSB), etc. The output range is +100%FS to –100.8%FS, where FS is 250pC. For the bipolar input range, the output code table changes with the use of Correlated Double Sampling (CDS). (There is no difference with or without CDS in the output code table when using the unipolar input range.
PAGE 23
Oversampling Control Samples/Integration—M - 4 bits CODE SAMPLES PER INTEGRATION 0000 0001 0010 0011 0100 0101 0110 0111 1XXX 1 2 4 8 16 32 64 128 256 Guard Pattern INTEGRATIONS PER CONVERSION 0000 0001 0010 0011 0100 0101 0110 0111 1XXX 1 2 4 8 16 32 64 128 256 INPUT RANGE 0 1 Unipolar Bipolar FIGURE 22. PC Board Layout Showing “Guard” Traces Surrounding Analog Input Pin and Traces. Power Supplies The ±5VDC supplies of the DDC101 should be bypassed with 10µF solid tantalum capacitors and 0.
PAGE 24
–5VDC 10µF Reference Buffer Bypass 0.1µF Analog Input +5VDC Guard 10µF 0.1µF 10Ω 0.1µF 1 VS– , ANALOG 24 2 ANALOG COMMON 23 3 ANALOG INPUT 22 4 ANALOG COMMON 21 5 VS+, ANALOG 20 6 VS+, ANALOG 19 7 18 8 17 9 16 10 15 11 14 12 VDD+, DIGITAL 13 REF1004 –2.5 10µF 1kΩ VREF –2.5V 10µF Reference Noise Filter Reference Bias Resistor 25kΩ VS– DIGITAL GROUND 24-Lead SOIC Top view Analog Common Digital Common FIGURE 24. Example of Basic DDC101 Circuit Connections.
PAGE 25
N Aquisition Time, K Time Clock Cycles Oversampled Initial Data Point X M Tracking Interval Final Data Point Start M Oversampled Final Data Point X Measurement Time Digital Output DDC101 digital output is precise integration of input during measurement time. FIGURE 25. DDC101 Equivalent Integrator Output for Single Integration with CDS.
PAGE 26
DATA INPUT DDC101 DATA OUTPUT DATA TRANSMIT In DATA INPUT DDC101 DATA TRANSMIT In DATA OUTPUT DATA INPUT DDC101 DATA OUTPUT DATA TRANSMIT In FIGURE 26. Daisy Chained DDC101s. DDC101 DATA INPUT DATA OUTPUT DATA TRANSMIT In DDC101 DATA INPUT Data Output DATA OUTPUT DATA TRANSMIT In DDC101 DATA INPUT DATA OUTPUT DATA TRANSMIT In Enable FIGURE 27. DDC101 Parallel Operation.
PAGE 27
FIGURE 28. Photo of DEM-DDC101P-C Evaluation Fixture. 25 Pin Cable PC Interface Board Your PC Analog Input DUT Board Assembly 34 Pin Cable ±5VDC +5VDC Power Supply FIGURE 29. DEM-DDC101P-C Evaluation Fixture Connection Diagram.
PAGE 28
PACKAGE OPTION ADDENDUM www.ti.com 7-Jan-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty DDC101U NRND SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DDC101UG4 NRND SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
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