Datasheet

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DDC112

Dual Current Input 20-Bit

ANALOG-TO-DIGITAL CONVERTER

FEATURES

● MONOLITHIC CHARGE MEASUREMENT A/D

CONVERTER

● DIGITAL FILTER NOISE REDUCTION:

3.2ppm, rms

● INTEGRAL LINEARITY:

±0.005% Reading ±0.5ppm FSR

● HIGH PRECISION, TRUE INTEGRATING FUNC-

TION

● PROGRAMMABLE FULL-SCALE

● SINGLE SUPPLY

● CASCADABLE OUTPUT

APPLICATIONS

● DIRECT PHOTOSENSOR DIGITIZATION

● CT SCANNER DAS

● INFRARED PYROMETER

● PRECISION PROCESS CONTROL

● LIQUID/GAS CHROMATOGRAPHY

● BLOOD ANALYSIS

DESCRIPTION

The DDC112 is a dual input, wide dynamic range, charge-

digitizing analog-to-digital (A/D) converter with 20-bit resolu-

tion. Low-level current output devices, such as photosensors,

can be directly connected to its inputs. Charge integration is

continuous as each input uses two integrators; while one is

being digitized, the other is integrating.

For each of its two inputs, the DDC112 combines current-to-

voltage conversion, continuous integration, programmable

full-scale range, A/D conversion, and digital filtering to achieve

a precision, wide dynamic range digital result. In addition to

the internal programmable full-scale ranges, external integrat-

ing capacitors allow an additional user-settable full-scale

range of up to 1000pC.

To provide single-supply operation, the internal A/D converter

utilizes a differential input, with the positive input tied to V

REF

When the integration capacitor is reset at the beginning of

each integration cycle, the capacitor charges to V

REF

. This

charge is removed in proportion to the input current. At the

end of the integration cycle, the remaining voltage is com-

pared to V

REF

The high-speed serial shift register which holds the result of

the last conversion can be configured to allow multiple DDC112

units to be cascaded, minimizing interconnections. The

DDC112 is available in an SO-28 or TQFP-32 package and is

offered in two performance grades.

Protected by US Patent #5841310

Dual

Switched

Integrator

Dual

Switched

Integrator

∆Σ

Modulator

Digital

Filter

Control

Digital

Input/Output

DVALID

DXMIT

DOUT

DIN

DCLK

RANGE2

RANGE1

RANGE0

TEST

CONV

CLK

CAP1A

CAP1B

CAP2A

CAP2B

IN2

IN1

REF

DGNDDV

AGNDAV

CHANNEL 1

CHANNEL 2

SBAS085B – JANUARY 2000 – REVISED OCTOBER 2004

www.ti.com

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

Summary of content (34 pages)

PAGE 1
DDC DD C11 2 112 DDC112 ® ® SBAS085B – JANUARY 2000 – REVISED OCTOBER 2004 Dual Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● MONOLITHIC CHARGE MEASUREMENT A/D CONVERTER ● DIGITAL FILTER NOISE REDUCTION: 3.2ppm, rms ● INTEGRAL LINEARITY: ±0.005% Reading ±0.
PAGE 2
ABSOLUTE MAXIMUM RATINGS(1) AVDD to DVDD ....................................................................... –0.3V to +6V AVDD to AGND ..................................................................... –0.3V to +6V DVDD to DGND ..................................................................... –0.3V to +6V AGND to DGND ............................................................................... ±0.3V VREF Voltage to AGND ........................................... –0.3V to AVDD + 0.
PAGE 3
ELECTRICAL CHARACTERISTICS At TA = +25°C, AVDD = DVDD = +5V, DDC112U, Y: TINT = 500µs, CLK = 10MHz, DDC112UK, YK: TINT = 333.3µs, CLK = 15MHz, VREF = +4.096V, continuous mode operation, and internal integration capacitors, unless otherwise noted.
PAGE 4
PIN CONFIGURATION PIN DESCRIPTIONS Top View SO IN1 1 28 IN2 AGND 2 27 AGND CAP1B 3 26 CAP2B CAP1B 4 25 CAP2B CAP1A 5 24 CAP2A CAP1A 6 23 CAP2A AVDD 7 22 VREF 21 AGND RANGE2 (MSB) PIN LABEL 1 IN1 2 AGND Analog Ground 3 CAP1B External Capacitor for Integrator 1B 4 CAP1B External Capacitor for Integrator 1B 5 CAP1A External Capacitor for Integrator 1A 6 CAP1A 7 AVDD Analog Supply, +5V Nominal 8 TEST Test Control Input.
PAGE 5
PIN CONFIGURATION 25 CAP2B 26 CAP2B 27 AGND 28 IN2 29 IN1 30 AGND 31 CAP1B TQFP 32 CAP1B Top View CAP1A 1 24 CAP2A CAP1A 2 23 CAP2A AVDD 3 22 VREF NC 4 21 AGND DDC112Y 16 RANGE1 RANGE0 (LSB) 17 15 8 DVALID CLK 14 RANGE2 (MSB) DOUT 18 13 7 DGND CONV 12 NC DVDD 19 11 6 DIN TEST 10 NC DXMIT 20 9 5 DCLK NC PIN DESCRIPTIONS PIN LABEL DESCRIPTION PIN LABEL DESCRIPTION 1 CAP1A External Capacitor for Integrator 1A 15 DVALID 2 CAP1A External Cap
PAGE 6
TYPICAL CHARACTERISTICS At TA = +25°C, characterization done with Range 5 (250pC), TINT = 500µs, VREF = +4.096, AVDD = DVDD = +5V, and CLK = 10MHz, unless otherwise noted. NOISE vs CSENSOR Noise (ppm of FSR, rms) 50 Range 2 Range 0 (CEXT = 250pF) 40 Noise (ppm of FSR, rms) Range 1 60 NOISE vs TINT 6 70 Range 7 30 20 5 CSENSOR = 50pF 4 CSENSOR = 0pF 3 2 Range 5 1 10 0 0 0 200 400 600 800 0.1 1000 1 10 4.5 8 CSENSOR = 50pF Noise (ppm of FSR, rms) Noise (ppm of FSR, rms) 9 3.
PAGE 7
TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, characterization done with Range 5 (250pC), TINT = 500µs, VREF = +4.096, AVDD = DVDD = +5V, and CLK = 10MHz, unless otherwise noted. OFFSET DRIFT vs TEMPERATURE INPUT VOS vs RANGE 36 100 All Ranges Offset Drift (ppm of FSR) 35 50 VOS (µV) 34 0 33 32 –50 31 30 –100 25 35 45 55 65 75 85 1 2 3 4 5 6 7 Range Temperature (°C) ANALOG SUPPLY CURRENT vs TEMPERATURE DIGITAL SUPPLY CURRENT vs TEMPERATURE 18 1.4 16 1.2 1.
PAGE 8
THEORY OF OPERATION The DVALID output goes LOW when the shift register contains valid data. The basic operation of the DDC112 is illustrated in Figure 1. The device contains two identical input channels where each performs the function of current-to-voltage integration followed by a multiplexed analog-to-digital (A/D) conversion. Each input has two integrators so that the current-to-voltage integration can be continuous in time.
PAGE 9
DEVICE OPERATION Basic Integration Cycle The fundamental topology of the front end of the DDC112 is a classical analog integrator, as shown in Figure 3. In this diagram, only Input 1 is shown. This representation of the input stage consists of an operational amplifier, a selectable feedback capacitor network (CF), and several switches that implement the integration cycle. The timing relationships of all of the switches shown in Figure 3 are illustrated in Figure 4.
PAGE 10
CONV CLK SINTA SINTB SREF1 SREF2 SRESET Integrate Convert Wait Wait Wait Reset Convert Wait Configuration of Integrator A Reset SA/D1A VREF Integrator A Voltage Output FIGURE 4. Basic Integrator Timing Diagram as Illustrated in Figure 3.
PAGE 11
Determining the Integration Capacitor (CF) Value EXTERNAL CAPACITOR PINS DDC112U, UK The value of the integrator’s feedback capacitor, the integration period, and the reference voltage determine the positive full-scale (+FS) value of the DDC112. The approximate positive full-scale value of the DDC112 is given by the following equations: 5 3 23 25 QFS = (0.
PAGE 12
A low-pass filter to reduce noise connects it to an operational amplifier configured as a buffer. This amplifier should have a unity-gain bandwidth greater than 4MHz, low noise, and input/output common-mode ranges that support VREF. Following the buffer are capacitors placed close to the DDC112 VREF pin. Even though the circuit in Figure 6 might appear to be unstable due to the large output capacitors, it works well for most operational amplifiers.
PAGE 13
TEST and CONV work together to implement this feature. The test mode is entered when TEST is HIGH prior to a CONV edge. At that point, a CONV edge triggers the grounding of the analog inputs and the switching of 13pC packets of charge onto the integration capacitors. If TEST is kept HIGH through at least two conversions (that is, a rise and fall of CONV), all four integrators will be charged with a 13pC packet.
PAGE 14
Table V can be easily found for a given CLK. For example, if CLK = 10MHz, then a CLK period = 0.1µs. t6 in Table V would then be 479.4µs. During the cont mode, mbsy is not active when CONV toggles. The non-integrating side is always ready to begin integrating when the other side finishes its integration. Consequently, keeping track of the current status of CONV is all that is needed to know the current state. Cont mode operation corresponds to states 3-6.
PAGE 15
Figure 11 shows the result of inverting the logic level of CONV. The only difference is in the first three states. Afterwards, the states toggle between 4 and 5 just as in the previous example. Figure 12 shows the timing diagram of the internal operations occurring during continuous mode operation. determines the boundary between the cont and ncont modes described earlier in the Overview section. DVALID goes LOW after CONV toggles in time t7, indicating that data is ready to be retrieved.
PAGE 16
Ncont Mode same time as in the cont mode. The second data will be ready in time t9 after the first data is ready. One result of the naming convention used in this application bulletin is that when the DDC112 is operating in the ncont mode, it passes through both ncont mode states and cont mode states. For example, in Figure 13, the state pattern is 3, 4, 1, 2, 3, 4, 1, 2, 3, 4...where 3 and 4 are cont mode states.
PAGE 17
Start Integration Side A Start Integration Side A End Integration Side A Start Integration Side B End Integration Side B Release State Wait State TINT t17 CONV TINT t16 A/D Conversion Input 1 t12 A/D Conversion Input 2 t12 t13 t15 DVALID Side A Data Ready Side B Data Ready FIGURE 14. Conversion Detail for the Internal Operation of the Non-Continuous Mode with Side A Integrated First.
PAGE 18
a 50% duty cycle CONV signal with TINT = 1620 CLK periods. Care must be exercised when using a square wave to generate CONV. There are certain integration times that must be avoided since they produce very short intervals for state 2 (or state 7 if CONV is inverted). As seen in the state diagram, the state progresses from 2 to 3 as soon as CONV is HIGH. The state machine does not insure that the duration of state 2 is long enough to properly prepare the next side for integration (t11).
PAGE 19
Changing Between Modes Changing from the ncont to cont mode occurs when TINT is increased so that TINT is always ≥ t6 (see Figure 14). With a longer TINT, the m/r/az cycle has enough time to finish before the next integration begins and continuous integration of the input signal is possible. For the special case of the very first integration when changing to the cont mode, TINT can be < t6.
PAGE 20
SPECIAL CONSIDERATIONS NCONT MODE INTEGRATION TIME The DDC112 uses a relatively fast clock. For CLK = 10MHz, this allows TINT to be adjusted in steps of 100ns since CONV should be synchronized to CLK. However, for the internal measurement, reset and auto-zero operations, a slower clock is more efficient. The DDC112 divides CLK by six and uses this slower clock with a period of 600ns to run the m/r/ az cycle and data ready logic.
PAGE 21
Sensor “F” Sensor “E” Sensor “D” IN2 IN1 Sensor “C” IN2 IN1 DDC112 RP DOUT “F” “E” DCLK DVALID DXMIT DIN 40 Bits IN2 DDC112 DCLK DVALID DXMIT Sensor “A” IN1 DDC112 DCLK DIN Sensor “B” “D” “C” DVALID DXMIT RP DOUT DIN 40 Bits “B” “A” RP DOUT Data Retrieval Outputs 40 Bits Data Retrievel Inputs FIGURE 20. Daisy-Chained DDC112s. DDC112 DIN DOUT DXMIT DDC112 Data Output DOUT DXMIT DIN DDC112 DOUT DXMIT DIN Enable FIGURE 21. DDC112 in Parallel Operation.
PAGE 22
CLK t18 t26 DVALID t14 DXMIT t20 DCLK(1) t22 t24 t25 DIN t22A, t22B t21 DOUT Output Disabled t23 Input A Bit 1 Input E Bit 20 Input F Bit 1 Input F Bit 20 MSB LSB MSB LSB Output Disabled Output Enabled NOTE: (1) Disable DCLK (preferably LOW) when DXMIT is HIGH. FIGURE 23. Timing Diagram When Using the DIN Function of the DDC112.
PAGE 23
CONV TINT TINT DVALID t27 t28 DXMIT DCLK ••• DOUT ••• ••• ••• Side B Data Side A Data CLK = 10MHz SYMBOL DESCRIPTION MIN t27 Cont Mode Data Ready t28 Data Retrieval Shutdown Before Edge of CONV TYP CLK = 15MHz MAX MIN 421.2 TYP MAX µs 280.8 10 UNITS µs 10 FIGURE 24. Readback Before CONV Toggles.
PAGE 24
RETRIEVAL BEFORE AND AFTER CONV TOGGLES (CONTINUOUS MODE) (available for download at www.ti.com), DVALID goes LOW in time t30 after the first integration completes. If TINT is shorter than this time, all of t31 is available to retrieve data before the other side’s data is ready. For TINT > t30, the first integration’s data is ready before the second integration completes. Data retrieval must be delayed until the second integration completes leaving less time available for retrieval.
PAGE 25
CONV TINT TINT TINT TINT DVALID t30 t31 DXMIT ••• DCLK ••• ••• ••• Side A Data Side B Data DOUT CLK = 10MHz SYMBOL DESCRIPTION t30 t31 1st Ncont Mode Data Ready (see SBAA024) 2nd Ncont Mode Data Ready (see SBAA024) MIN TYP CLK = 15MHz MAX MIN 421.1 ±0.3 454.8 TYP MAX UNITS µs µs 280.8 303.2 FIGURE 27. Readback in Noncontinuous Mode.
PAGE 26
Input shielding practices should be taken into consideration when designing the circuit layout for the DDC112. The inputs to the DDC112 are high impedance and extremely sensitive to extraneous noise. Leakage currents between the PCB traces can exceed the input bias current of the DDC112 if shielding is not implemented. Figure 30 illustrates an acceptable approach to this problem. A PC ground plane is placed around the inputs of the DDC112. This shield helps minimize coupled noise into the input pins.
PAGE 27
PACKAGE OPTION ADDENDUM www.ti.
PAGE 28
PACKAGE OPTION ADDENDUM www.ti.com 20-Aug-2011 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
PAGE 29
PACKAGE MATERIALS INFORMATION www.ti.com 7-Dec-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing DDC112U/1K SOIC DW 28 DDC112Y/250 TQFP PJT DDC112Y/2K TQFP PJT DDC112YK/250 TQFP PJT SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1 32 250 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2 32 2000 330.0 16.4 9.6 9.6 1.5 12.0 16.
PAGE 30
PACKAGE MATERIALS INFORMATION www.ti.com 7-Dec-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DDC112U/1K SOIC DW 28 1000 367.0 367.0 55.0 DDC112Y/250 TQFP PJT 32 250 367.0 367.0 38.0 DDC112Y/2K TQFP PJT 32 2000 367.0 367.0 38.0 DDC112YK/250 TQFP PJT 32 250 367.0 367.0 38.
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PAGE 32
PAGE 33
MECHANICAL DATA MPQF112 – NOVEMBER 2001 PJT (S-PQFP–N32) PLASTIC QUAD FLATPACK 0,45 0,30 0,80 0,20 M 0,20 0,09 Gage Plane 32 0,15 0,05 1 0,25 0°– 7° 7,00 SQ 0,75 0,45 9,00 SQ 1,05 0,95 Seating Plane 0,10 1,20 1,00 4203540/A 11/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
PAGE 34
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