Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External VQFN 48 Exposed Pad

FEATURES

D SINGLE-CHIP SOLUTION TO DIRECTLY

MEASURE EIGHT LOW-LEVEL CURRENTS

D HIGH PRECISION, TRUE INTEGRATING

FUNCTION

D INTEGRAL LINEARITY:

±0.01% of Reading ±0.5ppm of FSR

D VERY LOW NOISE: 5.2ppm of FSR

D LOW POWER: 13.5mW/channel

D ADJUSTABLE DATA RATE: Up to 3.125kSPS

D PROGRAMMABLE FULL SCALE

D DAISY-CHAINABLE SERIAL INTERFACE

Dual

Switched

Integrator

Dual

Switched

Integrator

∆Σ

Modulator

Digital

Filter

Digital

Input/Output

FORMAT

DCLK

DVALID

DOUT

DIN

Control

IN3

IN1

VREF DVDDAVDD

DGNDAGND

Dual

Switched

Integrator

Dual

Switched

Integrator

∆Σ

Modulator

Digital

Filter

IN4

IN2

Dual

Switched

Integrator

Dual

Switched

Integrator

∆Σ

Modulator

Digital

Filter

IN7

IN5

Dual

Switched

Integrator

Dual

Switched

Integrator

∆Σ

Modulator

Digital

Filter

IN8

IN6

CLK

CONV

RANGE0

RANGE1

RANGE2

TEST

CLK_4X

HISPD/LOPWR

RESET

APPLICATIONS

D CT SCANNER DAS

D PHOTODIODE SENSORS

D INFRARED PYROMETERS

D LIQUID/GAS CHROMATOGRAPHY

Protected by US Patent #5841310

DESCRIPTION

The DDC118 is a 20-bit, octal channel, current-input

analog-to-digital (A/D) converter. It combines both

current-to-voltage and A/D conversion so that eight

low-level current output devices, such as photodiodes, can

be directly connected to its inputs and digitized.

For each of the eight inputs, the DDC118 provides a

dual-switched integrator front-end. This design allows for

continuous current integration: while one integrator is

being digitized by the onboard A/D converter, the other is

integrating the input current. Adjustable full-scale ranges

from 12pC to 350pC and adjustable integration times from

50µs to 1s allow currents from fAs to µAs to be measured

with outstanding precision. Low-level linearity is ±0.5ppm

of the full-scale range and noise is 5.2ppm of the full-scale

range.

Two modes of operation are provided. In Low-Power

mode, total power dissipation is only 13.5mW per channel

with a maximum data rate of 2.5kSPS. High-Speed mode

supports data rates up to 3.125kSPS with a corresponding

dissipation of 18mW per channel.

The DDC118 has a serial interface designed for

daisy-chaining in multi-device systems. Simply connect

the output of one device to the input of the next to create

the chain. Common clocking feeds all the devices in the

chain so that the digital overhead in a multi-DDC118

system is minimal.

The DDC118 is a single-supply device using a +5V analog

supply and supporting a +2.7V to +5.25V digital supply.

Operating over the industrial temperature range of −40°C

to +85°C, the DDC118 is offered in a QFN-48 package.

DDC118

SBAS325B − JUNE 2004 − REVISED APRIL 2009

Octal Current Input, 20-Bit

Analog-To-Digital Converter

www.ti.com

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

         

          

 !     !   

Summary of content (35 pages)

PAGE 1
DDC118 SBAS325B − JUNE 2004 − REVISED APRIL 2009 Octal Current Input, 20-Bit Analog-To-Digital Converter FEATURES D D D D D D D D APPLICATIONS SINGLE-CHIP SOLUTION TO DIRECTLY MEASURE EIGHT LOW-LEVEL CURRENTS HIGH PRECISION, TRUE INTEGRATING FUNCTION INTEGRAL LINEARITY: ±0.01% of Reading ±0.5ppm of FSR VERY LOW NOISE: 5.2ppm of FSR LOW POWER: 13.5mW/channel ADJUSTABLE DATA RATE: Up to 3.
PAGE 2
""# www.ti.com SBAS325B − JUNE 2004 − REVISED APRIL 2009 ABSOLUTE MAXIMUM RATINGS(1) Analog Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750µA AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3V to +6V AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3V to +6V DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3V to +6V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 3
""# www.ti.com SBAS325B − JUNE 2004 − REVISED APRIL 2009 ELECTRICAL CHARACTERISTICS At TA = +25°C, AVDD = +5V, DVDD = 3V, VREF = +4.096V, Range 5 (250pC), and continuous mode operation, unless otherwise noted. Low-Power Mode: TINT = 400µs and CLK = 4MHz; High-Speed Mode: TINT = 320µs and CLK = 4.8MHz. Low-Power Mode PARAMETER TEST CONDITIONS ANALOG INPUT RANGE Range 0 Range 1 Range 2 Range 3 Range 4 Range 5 Range 6 Range 7 Negative Full-Scale Range Input Current(2) MIN TYP 10.2 12 13.8 47.5 50 52.
PAGE 4
""# www.ti.com SBAS325B − JUNE 2004 − REVISED APRIL 2009 ELECTRICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = +5V, DVDD = 3V, VREF = +4.096V, Range 5 (250pC), and continuous mode operation, unless otherwise noted. Low-Power Mode: TINT = 400µs and CLK = 4MHz; High-Speed Mode: TINT = 320µs and CLK = 4.8MHz.
PAGE 5
""# www.ti.
PAGE 6
""# www.ti.com SBAS325B − JUNE 2004 − REVISED APRIL 2009 TYPICAL CHARACTERISTICS At TA = +25°C, characterization done with Range 5 (250pC), AVDD = +5V, DVDD = 3V, VREF = +4.096V, and Low-Power Mode: TINT = 400µs and CLK = 4MHz, unless otherwise noted. NOISE vs CSENSOR NOISE vs CSENSOR 45 Noise (ppm of FSR, rms) Noise (ppm of FSR, rms) 40 CSENSOR Range Range Range Range Range Range Range Range (pF) 0 1 2 3 4 5 6 7 Range 1 35 0 23.6 7.3 5.2 4.4 4.2 4.0 3.8 3.7 24 30.8 10.4 6.7 5.
PAGE 7
""# www.ti.com SBAS325B − JUNE 2004 − REVISED APRIL 2009 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, characterization done with Range 5 (250pC), AVDD = +5V, DVDD = 3V, VREF = +4.096V, and Low-Power Mode: TINT = 400µs and CLK = 4MHz, unless otherwise noted. IB vs TEMPERATURE OFFSET DRIFT vs TEMPERATURE 10 100 Offset Drift (ppm of FSR) All Ranges IB (pA) 1 0.1 50 0 −50 −100 0.
PAGE 8
""# www.ti.com SBAS325B − JUNE 2004 − REVISED APRIL 2009 THEORY OF OPERATION The block diagram of the DDC118 is shown in Figure 1. The device contains eight identical input channels that perform the function of current-to-voltage integration followed by a multiplexed A/D conversion. Each input has two integrators so that the current-to-voltage integration can be continuous in time. The output of the sixteen integrators are switched to four delta-sigma (∆Σ) converters via four four-input multiplexers.
PAGE 9
""# www.ti.com SBAS325B − JUNE 2004 − REVISED APRIL 2009 The digital interface of the DDC118 provides the digital results via a synchronous serial interface consisting of differential data clocks (DCLK and DCLK), a valid data pin (DVALID), differential serial data output pins (DOUT and DOUT), and differential serial data input pins (DIN and DIN). The DDC118 contains only four A/D converters, so the conversion process is interleaved (see Figure 2).
PAGE 10
""# www.ti.com SBAS325B − JUNE 2004 − REVISED APRIL 2009 CONV CLK SINTA SINTB SREF1 SREF2 SRESET Integrate Convert Wait W a it Wait R e se t Convert W a it Configuration of Integrator A R e se t SA/D1A VREF Integrator A Voltage Output Figure 4.
PAGE 11
""# www.ti.com SBAS325B − JUNE 2004 − REVISED APRIL 2009 Voltage Reference At the completion of an A/D conversion, the charge on the integration capacitor (CF) is reset with SREF1 and SRESET (see Figure 4 and Figure 5a). In this manner, the selected capacitor is charged to the reference voltage, VREF. Once the integration capacitor is charged, SREF1 and SRESET are switched so that VREF is no longer connected to the amplifier circuit while it waits to begin integrating (see Figure 5b).
PAGE 12
""# www.ti.com SBAS325B − JUNE 2004 − REVISED APRIL 2009 DDC118 Frequency Response Test Mode The frequency response of the DDC118 is set by the front end integrators and is that of a traditional continuous time integrator, as shown in Figure 7. By adjusting TINT, the user can change the 3dB bandwidth and the location of the notches in the response.
PAGE 13
""# www.ti.com SBAS325B − JUNE 2004 − REVISED APRIL 2009 DIGITAL INTERFACE The digital interface of the DDC118 provides the digital results via a synchronous serial interface consisting of differential data clocks (DCLK and DCLK), a valid data pin (DVALID), differential serial data output pins (DOUT and DOUT), and differential serial data input pins (DIN and DIN). The DDC118 contains only four A/D converters, so the conversion process is interleaved (see Figure 2, page 9).
PAGE 14
""# www.ti.com SBAS325B − JUNE 2004 − REVISED APRIL 2009 Conversion Rate The conversion rate of the DDC118 is set by a combination of the integration time (determined by the user) and the speed of the A/D conversion process. The A/D conversion time is primarily a function of the system clock (CLK) speed.
PAGE 15
""# www.ti.com SBAS325B − JUNE 2004 − REVISED APRIL 2009 TIMING EXAMPLES measurement cycles are underway. The internal signal mbsy is shown next. Finally, DVALID is given. DVALID goes active low when data is ready to be retrieved from the DDC118. It stays low until DCLK is taken high and then back low by the user. The text below the DVALID pulse indicates the side of the data available to be read, and arrows help match the data to the corresponding integration.
PAGE 16
""# www.ti.com SBAS325B − JUNE 2004 − REVISED APRIL 2009 End Integration Side B Start Integration Side A End Integration Side A Start Integration Side B TINT CONV TINT Side A A/D Conversion Inputs 1, 2, 5, and 6 (Internal) End Integration Side A Start Integration Side B Side A t14 Side B t12 Side A A/D Conversion Inputs 3, 4, 7, and 8 (Internal) Side B t 13 t12 t 13 t 14 DVALID Side A Data Ready Side B Data Ready Figure 12.
PAGE 17
""# www.ti.com SBAS325B − JUNE 2004 − REVISED APRIL 2009 Ncont Mode Non-continuous mode of operation is intended for Ranges 1 to 7. It is not recommended to use Range 0 when operating in non-continuous mode. Figure 13 illustrates operation in the ncont mode. The integrations come in pairs (that is, sides A/B or sides B/A) followed by a time during which no integrations occur. During that time, the previous integrations are being measured, reset and auto-zeroed.
PAGE 18
""# www.ti.com SBAS325B − JUNE 2004 − REVISED APRIL 2009 Start Integration Side A Start Integration Side A End Integration Side A Start Integration Side B End Integration Side B Release State Wait State TINT t17 CONV TINT t 16 A/D Conversion Inputs 1, 2, 5, and 6 t12 A/D Conversion Inputs 3, 4, 7, and 8 t12 t13 t 15 DVALID Side A Data Ready Side B Data Ready Figure 14. Conversion Detail for the Internal Operation of Non-Continuous Mode with Side A Integrated First Table 8.
PAGE 19
""# www.ti.com SBAS325B − JUNE 2004 − REVISED APRIL 2009 cycle CONV signal with TINT = 512 CLK periods. Care must be exercised when using a square wave to generate CONV. There are certain integration times that must be avoided since they produce very short intervals for state 2 (or state 7 if CONV is inverted). As seen in the state diagram, the state progresses from 2 to 3 as soon as CONV is high.
PAGE 20
""# www.ti.com SBAS325B − JUNE 2004 − REVISED APRIL 2009 Changing Between Modes Changing from the ncont to cont mode occurs when TINT is increased so that TINT is always ≥ t6, as shown in Figure 19 (see also Figure 14 and Table 8, page 18). With a longer TINT, the m/r/az cycle has enough time to finish before the next integration begins and continuous integration of the input signal is possible. For the special case of the very first integration when changing to the cont mode, TINT can be < t6.
PAGE 21
""# www.ti.com SBAS325B − JUNE 2004 − REVISED APRIL 2009 DATA FORMAT (FORMAT) DATA RETRIEVAL The serial output data is provided in an offset binary code as shown in Table 9. The digital input pin FORMAT selects how many bits are used in the output word. When FORMAT is high (1), 20 bits are used. When FORMAT is low (0), the lower 4 bits are truncated so that only 16 bits are used. Note that the LSB size is 16 times bigger when FORMAT = 0.
PAGE 22
""# www.ti.com SBAS325B − JUNE 2004 − REVISED APRIL 2009 DDC118 devices together to minimize wiring. In this mode of operation, the serial data output is shifted through multiple DDC118s, as illustrated in Figure 21. SPECIAL CONSIDERATIONS Cascading Multiple Converters Multiple DDC118 units can be connected in serial configuration, as illustrated in Figure 21. See Figure 22 for the timing diagram when the DIN input is used to daisy-chain several devices.
PAGE 23
""# www.ti.com SBAS325B − JUNE 2004 − REVISED APRIL 2009 RETRIEVAL BEFORE CONV TOGGLES (CONTINUOUS MODE) NOTE: 128τDCLK is used for FORMAT = low. where τDCLK is the period of the data clock. For example, if TINT = 1000µs and DCLK = 10MHz, the maximum number of DDC118s (FORMAT = high) is shown in Equation 2: Date retrieval before CONV toggles is the most straightforward method. Data retrieval begins soon after DVALID goes low and finishes before CONV toggles, as shown in Figure 23.
PAGE 24
""# www.ti.com SBAS325B − JUNE 2004 − REVISED APRIL 2009 RETRIEVAL AFTER CONV TOGGLES (CONTINUOUS MODE) of DDC118s that can be daisy-chained together (FORMAT = high) is calculated by Equation 3: For shorter integration times, more time is available if data retrieval begins after CONV toggles and ends before the new data is ready. Data retrieval must wait t29 after CONV toggles before beginning. See Figure 24 for an example of this. The maximum time available for retrieval is t27 − t29 – t26 (344.
PAGE 25
""# www.ti.com SBAS325B − JUNE 2004 − REVISED APRIL 2009 RETRIEVAL BEFORE AND AFTER CONV TOGGLES (CONTINUOUS MODE) RETRIEVAL: NONCONTINUOUS MODE Retrieving in noncontinuous mode is slightly different, compared to the continuous mode. As illustrated in Figure 26, DVALID goes low in time t30 after the first integration completes. If TINT is shorter than this time, all of t31 is available to retrieve data before the other side data is ready.
PAGE 26
""# www.ti.com SBAS325B − JUNE 2004 − REVISED APRIL 2009 POWER-UP SEQUENCING Prior to power-up, all digital and analog inputs must be low. After the power supplies have settled, release RESET after time t32. (See Figure 28 and Table 12.) Wait for time t33 to begin applying the digital signals CONV and CLK. The first CONV pulse will complete the release state and begin integration. VA AVDD 10µF DDC118 VD DVDD LAYOUT AGND 0.1µF 10µF DGND 0.
PAGE 27
""# www.ti.com SBAS325B − JUNE 2004 − REVISED APRIL 2009 Shielding Analog Signal Paths currents between the PCB traces can exceed the input bias current of the DDC118 if shielding is not implemented. Figure 29 illustrates an acceptable approach to this problem. A PC ground plane is placed around the inputs of the DDC118. This shield helps minimize coupled noise into the input pins. As with any precision circuit, careful PCB layout ensures the best performance.
PAGE 28
www.ti.com SBAS325B − JUNE 2004 − REVISED APRIL 2009 Revision History DATE REV 4/09 B PAGE SECTION 1 Front Page 9 Theory of Operation DESCRIPTION Updated front page appearance. Changed last sentence of first paragraph on page 9. NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
PAGE 29
PACKAGE OPTION ADDENDUM www.ti.
PAGE 30
PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DDC118IRTCR VQFN RTC 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 DDC118IRTCT VQFN RTC 48 250 330.0 16.4 7.3 7.3 1.5 12.0 16.
PAGE 31
PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DDC118IRTCR VQFN RTC 48 2500 336.6 336.6 28.6 DDC118IRTCT VQFN RTC 48 250 336.6 336.6 28.
PAGE 32
PAGE 33
PAGE 34
PAGE 35
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.