Network Router User Manual

Data Valid
11
SPISOMI
SPISIMO
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
Master In Data
Must Be Valid
Master Out Data Is Valid
1
7
6
10
3
2
SPISTE
(see Note A)
SM320F2812-HT
SGUS062A–JUNE 2009 –REVISED APRIL 2010 www.ti.com
A. In the master mode, SPISTE goes active 0.5tc(SPC) before valid SPI clock edge. On the trailing end of the word, the
SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6-25. SPI Master External Timing (Clock Phase = 1)
112 Electrical Specifications Copyright © 2009–2010, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320F2812-HT