Datasheet

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FEATURES APPLICATIONS

DESCRIPTION

DIR9001

SLES198 – DECEMBER 2006

96-kHz, 24-Bit Digital Audio Interface Receiver

• AV/DVD Receiver, AV Amplifier

• One-Chip Digital Audio Interface Receiver

(DIR) Including Low-Jitter Clock-Recovery

• Car or Mobile Audio System

System

• Digital Television

• Compliant With Digital Audio Interface

• Musical Instruments

Standards: IEC60958 (former IEC958), JEITA

• Recording Systems

CPR-1205 (former EIAJ CP-1201, CP-340),

• High-End Audio/Sound Card for PC

AES3, EBU tech3250

• Replacement of DIR1703

• Clock Recovery and Data Decode From

• Other Applications Requiring S/PDIF Receiver

Biphase Input Signal, Generally Called S/PDIF,

EIAJ CP-1201, IEC60958, AES/EBU

• Biphase Input Signal Sampling Frequency (f

)

The DIR9001 is a digital audio interface receiver that

Range: 28 kHz to 108 kHz

can receive a 28-kHz to 108-kHz sampling-

• Low-Jitter Recovered System Clock: 50 ps

frequency, 24-bit-data-word, biphase-encoded signal.

The DIR9001 complies with IEC60958-3, JEITA

• Jitter Tolerance Compliant With IEC60958-3

CPR-1205 (Revised version of EIAJ CP-1201),

• Selectable Recovered System Clock: 128 f

AES3, EBUtech3250, and it can be used in various

256 f

, 384 f

, 512 f

applications that require a digital audio interface.

• Serial Audio Data Output Formats: 24-Bit I

The DIR9001 supports many output system clock

MSB-First, 24-Bit Left-Justified; MSB-First 16-,

and output data formats and can be used flexibly in

24-Bit Right-Justified

many application systems. As the all functions which

• User Data, Channel-Status Data Outputs

the DIR9001 provides can be controlled directly

Synchronized With Decoded Serial Audio Data

through control pins, it can be used easily in an

application system that does not have a

• No External Clock Required for Decode

microcontroller. Also, as dedicated pins are provided

• Includes Actual Sampling Frequency

for the channel-status bit and user-data bit,

Calculator (Needs External 24.576-MHz Clock)

processing of their information can be easily

• Function Control: Parallel (Hardware)

accomplished by connecting with a microcontroller,

DSP, etc.

• Functions Similar and Pin Assignments

Equivalent to Those of DIR1703

The DIR9001 does not require an external clock

source or resonator for decode operation if the

• Single Power Supply: 3.3 V (2.7 V to 3.6 V)

internal actual-sampling-frequency calculator is not

• Wide Operating Temperature Range: –40 ° C to

used. Therefore, it is possible to reduce the cost of a

85 ° C

system.

• 5 V-Tolerant Digital Inputs

The operating temperature range of the DIR9001 is

• Package: 28-pin TSSOP, Pin Pitch: 0,65 mm

specified as –40 ° C to 85 ° C, which makes it suitable

for automotive applications.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SpAct is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (34 pages)

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DIR9001 SLES198 – DECEMBER 2006 96-kHz, 24-Bit Digital Audio Interface Receiver FEATURES APPLICATIONS • • • • • • • • • • • • • • • • • • • • • • • • • One-Chip Digital Audio Interface Receiver (DIR) Including Low-Jitter Clock-Recovery System Compliant With Digital Audio Interface Standards: IEC60958 (former IEC958), JEITA CPR-1205 (former EIAJ CP-1201, CP-340), AES3, EBU tech3250 Clock Recovery and Data Decode From Biphase Input Signal, Generally Called S/PDIF
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DIR9001 www.ti.com SLES198 – DECEMBER 2006 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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DIR9001 www.ti.com SLES198 – DECEMBER 2006 ELECTRICAL CHARACTERISTICS All specifications at TA = 25°C, VDD = VCC = 3.3 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUT/OUTPUT CHARACTERISTICS VIH VIL VIH VIL VOH VOL IIH IIL IIH IIL IIH IIL 0.7 VDD Input logic level (1) 0.3 VDD 2 Input logic level (2) Output logic level (3) Input leakage current (4) Input leakage current (5) Input leakage current (6) VDD 5.5 0.8 IO = 4 mA 0.85 VDD IO = –4 mA 0.
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DIR9001 www.ti.com SLES198 – DECEMBER 2006 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VDD = VCC = 3.3 V (unless otherwise noted) PARAMETER ICC Supply current (7) TEST CONDITIONS MIN TYP MAX fS = 96 kHz, PLL locked, XTI connected to DGND 6 8.3 mA fS = 96 kHz, PLL locked, XTI connected to 24.576-MHz resonator 6 8.
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DIR9001 www.ti.com SLES198 – DECEMBER 2006 TERMINAL FUNCTIONS TERMINAL NAME NO.
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DIR9001 www.ti.
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DIR9001 www.ti.com SLES198 – DECEMBER 2006 TYPICAL PERFORMANCE CHARACTERISTICS Oscillation amplifier operating with crystal; 1-kHz, 0-dB, sine-wave data; no load POWER SUPPLY CURRENT SUPPLY CURRENT vs LOCKED SAMPLING FREQUENCY SUPPLY CURRENT vs LOCKED SAMPLING FREQUENCY 20 20 VCC = VDD = 3.3 V SCKO = 256 fS 18 ICC + IDD − Supply Current − mA ICC + IDD − Supply Current − mA 18 TA = 255C SCKO = 256 fS 16 14 85°C 12 –40°C 50°C 25°C –25°C 10 0°C 16 14 3.3 V 3.6 V 12 10 2.
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DIR9001 www.ti.com SLES198 – DECEMBER 2006 DEVICE INFORMATION ACCEPTABLE BIPHASE INPUT SIGNAL AND BIPHASE INPUT PIN (RXIN) The DIR9001 can decode the biphase signal format which is specified in one of the following standards. Generally, these following standards may be called Sony/Philips digital interface format (S/PDIF) or AES/EBU.
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DIR9001 www.ti.com SLES198 – DECEMBER 2006 DEVICE INFORMATION (continued) SYSTEM RESET The DIR9001 reset function is controlled by and external reset pin, RST. The reset operation must be performed during the power-up sequence as shown in Figure 4. Specifically, the DIR9001 requires reset operation with a 100-ns period after the supply voltage rises above 2.7 V. 2.7 V VDD RST DIR9001 Status Unknown Reset Operation Min. 100 ns Figure 4.
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DIR9001 www.ti.com SLES198 – DECEMBER 2006 OPERATION MODE AND CLOCK TRANSITION SIGNAL OUT Operation Mode The DIR9001 has the following three operation modes. These modes are selected by the connection of the CKSEL pin. • PLL MODE: For demodulating a biphase input signal; always outputs PLL source clock • XTI MODE: For clock generator; always outputs XTI source clock • AUTO MODE: Automatic clock source selection; output source depends on ERROR pin.
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DIR9001 www.ti.com SLES198 – DECEMBER 2006 FILT XTI XTO OSC Sampling Frequency Calculator FSOUT0 FSOUT1 Clock and Data Recovery SCKO RXIN Preamble Detector Charge Pump VCO Divider PLL BCKO Divider Clock Decoder LRCKO Biphase Data Decoder ERROR Detector ERROR CLKST Decoder CKSEL Serial Audio Data Formatter Audio Data MUTE Control DOUT DGND Figure 5.
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DIR9001 www.ti.
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DIR9001 www.ti.com SLES198 – DECEMBER 2006 CLOCK DESCRIPTION System Clock Source DIR9001 has the following two clock sources for the system clock. • PLL source (128 fS, 256 fS, 384 fS, 512 fS are available, recovered by built-in PLL) • XTI source (One 24.576-MHz resonator or external clock source is required.) Two clock sources are used for the following purpose.
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DIR9001 www.ti.com SLES198 – DECEMBER 2006 [PSCK1] [PSCK0] VCO RXIN 1/N CKSEL (I) Built-in PLL Clock Recovery 1/N SCKO (O) 1/N PLL Clock Source BCKO (O) XTI (I) LRCKO (O) 1/4 XTO (O) Oscillation Amplifier Clock Source Selector 1/64 XTI Clock Source Figure 7. Clock Tree Diagram PLL Clock Source (Built-In PLL and VCO) Description The DIR9001 has on-chip PLL (including VCO) for recovering the clock from the biphase input signal.
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DIR9001 www.ti.com SLES198 – DECEMBER 2006 In PLL mode (CKSEL = L), output clocks (SCKO, BCKO, LRCKO) are generated from the PLL source clock. The relationship between frequencies of LRCKO, BCKO, and SCKO at different sampling frequencies fS of the biphase input signal are shown in Table 4. Table 4. Output Clock Frequency in PLL Locked State (CKSEL = L) LRCKO BCKO fS 64 fS SCKO (Depending on PSCK[1:0] Setting) 128 fS 256 fS 384 fS 512 fS 32 kHz 2.048 MHz 4.096 MHz 8.192 MHz 12.288 MHz 16.
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DIR9001 www.ti.com SLES198 – DECEMBER 2006 XTI Clock Source and Oscillation Amplifier Description This clock, driven by the built-in oscillation amplifier or input into the XTI pin from an external clock, is defined as the XTI source. A 24.576-MHz fundamental resonator or external 24.576-MHz clock is used as the XTI source.
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DIR9001 www.ti.com SLES198 – DECEMBER 2006 DATA DESCRIPTION Decoded Serial Audio Data Output and Interface Format The DIR9001 supports following 4-data formats for the decoded data. • 16-bit, MSB-first, right-justified • 24-bit, MSB-first, right-justified • 24-bit, MSB-first, left-justified • 24-bit, MSB-first, I2S Decoded data is MSB first and 2s-complement in all formats. The decoded data is provided through the DOUT pin. The format of the decoded data is selected by the FMT[1:0] pins.
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DIR9001 www.ti.com SLES198 – DECEMBER 2006 The relationships among BCKO, LRCKO, and DOUT for each format are shown in Figure 11.
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DIR9001 www.ti.com SLES198 – DECEMBER 2006 tSCY tSCBC SCKO (OUT) VDD/2 LRCKO (OUT) VDD/2 tBCH tBCL tCKLR BCKO (OUT) VDD/2 tBCY tBCDO DOUT (OUT) VDD/2 PARAMETERS MIN TYP MAX UNIT tSCY System clock pulse cycle time 18 tSCBC Delay time of SCK rising edge to BCK rising edge 4 8 15 ns ns tCKLR Delay time of BCKO falling edge to LRCKO valid –5 0.5 0.
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DIR9001 www.ti.com SLES198 – DECEMBER 2006 Channel-Status Data and User Data Serial Outputs The DIR9001 can output channel-status data and user data synchronized with audio data from the biphase input signal. Each output data has its own dedicated output pin. • Channel-status data (C, hereinafter) is output through COUT pin. • User data (U, hereinafter) is output through UOUT pin. The C and U outputs are synchronized with LRCKO recovered from the biphase input signal.
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DIR9001 www.ti.com SLES198 – DECEMBER 2006 AUDIO Pin This is the output pin for the audio sample word information of the channel-status data bit 1. Table 8. Audio Sample Word Information AUDIO DESCRIPTION L Audio sample word represents linear PCM samples. H Audio sample word is used for other purposes. EMPH Pin This is the output pin for the emphasis information of the channel-status data bit 3. Table 9.
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DIR9001 www.ti.com SLES198 – DECEMBER 2006 ERRORS AND ERROR PROCESSING Error Output Description Error detection and data error processing for PLL errors • PLL responds with unlock for data in which the rule of biphase encoding is lost (biphase error and frame-length error). • PLL responds with unlock for data in which the preamble B, M, W can not be detected. Error processing function and error output pins • The DIR9001 has a data error detect function and an error output pin, ERROR.
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DIR9001 www.ti.com SLES198 – DECEMBER 2006 [AUDIO = L] Internal LOCK AUDIO 2 LRCKO (I S) ERROR DOUT MUTE (Low) Ln Rn Ln+1 Rn+1 Ln+1 Rn+2 Ln+3 Rn+3 Interpolation Processing by Previous Data [AUDIO = H] Parity Error Internal LOCK AUDIO 2 LRCKO (I S) ERROR DOUT MUTE (Low) Ln Rn Ln+1 Rn+1 Ln+2 Rn+2 Ln+3 Rn+3 Parity Error Figure 16.
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DIR9001 www.ti.com SLES198 – DECEMBER 2006 CALCULATION OF ACTUAL SAMPLING FREQUENCY The DIR9001 calculates the actual sampling frequency of the biphase input signal and outputs its result through dedicated pins. To use this function, a 24.576-MHz clock source must be supplied to the XTI pin. The 24.576-MHz clock is used as a measurement reference clock to calculate the actual sampling frequency. If the XTI pin is connected to DGND, calculation of the actual sampling frequency is not performed.
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DIR9001 www.ti.com SLES198 – DECEMBER 2006 TYPICAL CIRCUIT CONNECTION Figure 17 illustrates typical circuit connection. For Automatic Clock Source Selection Actual Sampling Frequency Output 3.3-V VDD + C5 CKSEL 28 FSOUT0 ERROR 27 3 FSOUT1 FMT1 26 4 SCKO FMT0 25 5 VDD VCC 24 1 AUDIO 2 C6 + C7 6 DGND 7 X1 C4 C8 3.
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DIR9001 www.ti.com SLES198 – DECEMBER 2006 APPLICATION INFORMATION Differences for DIR1703 The DIR9001 has many improved functions compared to the DIR1703. The DIR9001 functions are similar to those of the DIR1703. The DIR9001 pin assignment is equivalent to that of the DIR1703. The DIR9001 biphase input signal decoding function is almost equivalent to that of the DIR1703. The differences between the DIR9001 and DIR1703 are shown in Table 12. Table 12.
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DIR9001 www.ti.com SLES198 – DECEMBER 2006 The differences between the DIR1703 and DIR9001 I/O pins are shown in Table 13. Table 13. The Differences Between DIR1703 and DIR9001 in All I/O Pin PIN NO.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device DIR9001PWR Package Package Pins Type Drawing TSSOP PW 28 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.2 1.8 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DIR9001PWR TSSOP PW 28 2000 367.0 367.0 38.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.