Datasheet

DIT4096
12
SBOS225A
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CONTROL REGISTER DEFINITIONS
(SOFTWARE MODE ONLY)
This section defines the control registers used to configure
the DIT4096, as well as the status register used to indicate
an interrupt source.
When MONO = 1 and MCSD = 0, the MDAT bit
is used to select the source for Audio data.
When MONO = 1 and MCSD = 1, the MDAT bit
is used to select the source for both Audio and
Channel Status data.
MCSD Channel Status Data Selection (Defaults to 0)
When set to 0, Channel A data is used for the A
sub-frame, while Channel B data is used for the
B sub-frame.
When set to 1, use the same channel status data
for both A and B sub-frames. Channel status
data source is selected using the MDAT bit.
TXOFF Transmitter Output Disable (Defaults to 0)
When set to 0, the line driver outputs, TX–
(pin 17) and TX+ (pin 18) are enabled.
When set to 1, the line driver outputs are
forced to ground.
MUTE Transmitter Mute (Defaults to 0)
When set to 0, the mute function is disabled.
When set to 1, the mute function is enabled,
with Channel A and B audio data set to all 0’s.
BYPASS Transmitter Bypass—AES-3 Data Source for
the Output Driver (Defaults to 0)
When set to 0, AES-3 encoded data is taken
from the output of the on-chip encoder.
When set to 1, RXP (pin 9) is used as the
source for AES-3 encoded data.
MONO Mono Mode Control (Defaults to 0)
When set to 0, the transmitter is set to Stereo
mode.
When set to 1, the transmitter is set to Mono
mode.
MDAT Data Selection Bit (Defaults to 0)
(0 = Left Channel, 1 = Right Channel)
When MONO = 0 and MCSD = 0, the MDAT bit
is ignored.
When MONO = 0 and MCSD = 1, the MDAT bit
is used to select the source for Channel
Status data.
PDN Power-Down (Defaults to 1)
When set to 0, the DIT4096 operates normally.
When set to 1, the DIT4096 is powered down,
with the line driver outputs forced to ground.
CLK[1:0] MCLK Rate Selection
These bits are used to select the master clock
frequency applied to the MCLK input (pin 6).
CLK1 CLK0 MCLK Rate
0 0 Unused
0 1 256 • f
S
(default)
1 0 384 • f
S
1 1 512 • f
S
RST Software Reset (Defaults to 0)
When set to 0, the DIT4096 operates normally.
When set to 1, the DIT4096 is reset.
M/S Master/Slave Mode (Defaults to 0)
When set to 0, the audio serial port is set for
Slave operation.
When set to 1, the audio serial port is set for
Master operation.
BLSM Block Start Mode (Defaults to 0)
When set to 0, BLS (pin 25) is configured as an
input pin.
When set to 1, BLS (pin 25) is configured as an
output pin.
VAL Audio Data Valid (Defaults to 0)
When set to 0, valid Linear PCM audio data is
indicated.
When set to 1, invalid audio data or non-PCM
data is indicated.
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
0 0 0 0 RST CLK1 CLK0 PDN
Register 02
H
: Power-Down and Clock Control Register
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
ISYNC ISCLK DELAY JUS WLEN1 WLEN0 SCLKR M/S
Register 03
H
: Audio Serial Port Control Register
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
TXOFF MCSD MDAT MONO BYPAS MUTE VAL BLSM
Register 01
H
: Transmitter Control Register
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
00000000
Register 00
H
: Reserved for Factory Use