Datasheet

DIT4096
13
SBOS225A
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SCLKR Master Mode SCLK Frequency (Defaults to 0)
When set to 0, the SCLK frequency is set to
64 • f
S
.
When set to 1, the SCLK frequency is set to
128 • f
S
.
WLEN[1:0] Audio Data Word Length
These bits are used to set the audio data word
length for both Left and Right channels.
WLEN1 WLEN0 Length
0 0 24 Bits (default)
0 1 20 Bits
1 0 18 Bits
1 1 16 Bits
JUS Audio Data Justification (Defaults to 0)
When set to 0, the audio data is Left-Justified
with respect to the SYNC edges.
When set to 1, the audio data is Right-Justified
with respect to the SYNC edges.
DELAY Audio Data Delay from the Start of Frame
(Defaults to 0)
This applies primarily to I
2
S and DSP frame
formats, which use Left-Justified audio data.
When set to 0, audio data starts with the SCLK
period immediately following the SYNC edge
which starts the frame. This is referred to as a
zero SCLK delay.
When set to 1, the audio data starts with the
second SCLK period following the SYNC edge
which starts the frame. This is referred to as a
one SCLK delay. This is used primarily for the
I
2
S data format.
ISCLK SCLK Sampling Edge (Defaults to 0)
When set to 0, audio serial data at SDATA
(pin 13) is sampled on rising edge of SCLK.
When set to 1, audio serial data at SDATA
(pin 13) is sampled on falling edge of SCLK.
ISYNC SYNC Polarity (Defaults to 0)
When set to 0, Left channel data occurs when
the SYNC clock is HIGH.
When set to 1, Left channel data occurs when
the SYNC clock is LOW.
For both cases, Left channel data always pre-
cedes the Right channel data in the audio frame.
BTI Buffer Transfer Interrupt Status—Active
High
When User Access (UA) to Transmitter Access
(TA) buffer transfers are enabled, and the BTI
interrupt is unmasked, this bit will go HIGH
when a UA to TA buffer transfer has com-
pleted. This will also cause the INT
output
(pin 22) to be driven LOW, indicating that an
interrupt has occurred.
TSLIP Transmitter Source Data Slip Interrupt Sta-
tus—Active High
This bit will go HIGH when either a Data Slip or
Block Start condition is detected, and the TSLIP
interrupt is unmasked. This will also cause the
INT
output (pin 22) to be driven LOW, indicat-
ing that an interrupt has occurred. The function
of this bit is selected using the BSSL bit in
control register 05
H
(defaults Data Slip).
The MBTI and MTSLIP bits are used to mask
the BTI and TSLIP interrupts. When masked,
these interrupt sources are disabled.
MBTI BTI Interrupt Mask. Set to ‘0’ to mask BTI
(Defaults to 0).
MTSLIP TSLIP Interrupt Mask. Set to ‘0’ to mask
TSLIP (Defaults to 0).
BSSL TSLIP Interrupt Select (Defaults to 0)
When set to 0, the Data Slip condition is used
to trigger a TSLIP interrupt.
When set to 1, the Block Start condition is
used to trigger a TSLIP interrupt.
BTIM[1:0] BTI Interrupt Mode
TSLIPM[1:0] TSLIP Interrupt Mode
These bits are used to select the active state
for interrupt operation.
BTIM1 or BTIM0 or
TSLIPM1 TSLIPM0 Interrupt Operation
0 0 Rising Edge Active (default)
0 1 Falling Edge Active
1 0 Level Active
1 1 Reserved
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
0 0 0 0 0 0 TSLIP BTI
Register 04
H
: Interrupt Status Register
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
0 0 0 0 0 BSSL MTSLIP MBTI
Register 05
H
: Interrupt Mask Register
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
0 0 0 0 TSLIPM1 TSLIPM0 BTIM1 BTIM0
Register 06
H
: Interrupt Mode Register