Datasheet

DIT4096
14
SBOS225A
www.ti.com
BTD Buffer Transfer Disable (Defaults to 0)
When set to 0, User Access (UA) to Transmit-
ter Access (TA) Buffer transfers are enabled.
When set to 1, User Access (UA) to Transmit-
ter Access (TA) Buffer transfers are disabled.
The master clock input (MCLK) and the frame synchroniza-
tion clock input (SYNC) muct be active in order to update the
channel status buffer in Software mode. When the DIT4096
is initially powered up, the device defaults to power-down
mode. When the PDN bit in Register 2 is set to 0 to power
up the device, there must be a delay between the time that
PDN is set to 0 and the first access to the channel status
buffer. This delay allows the SYNC clock to synchronize the
AES3 encoder block with the audio serial port. It is recom-
mended that Register 2 be the last register written in the
initialization sequence, followed by a delay (10 milliseconds
or longer) before attempting to access the channel status
buffer.
UPDATING THE CHANNEL DATA STATUS BUFFER
Updating the channel status data buffer involves disabling
and enabling the UA to TA buffer transfer using the BTD bit
in control register 07
H
. Figure 9 shows the proper flow for
updating the buffer.
The BTD bit is normally set to 0, which enables the UA to TA
buffer transfer. In order to update the channel status data,
the user must write to the UA buffer. To avoid UA to TA data
transfer while the UA buffer is being updated, the BTD bit is
set to 1, which disables UA to TA buffer transfers. While
BTD = 1, the user writes new channel status data to the UA
buffer via the control port. Once the UA buffer update is
complete, the BTD bit is reset to 0. A new UA to TA buffer
transfer will occur during one of the frames 184 through 191,
CHANNEL STATUS DATA
BUFFER OPERATION
(SOFTWARE MODE ONLY)
The DIT4096 contains two buffers for the channel status data.
These are referred to as the Transmitter Access (TA) buffer
and the User Access (UA) buffer. Each buffer is 48 bytes long,
containing 24 bytes each for channels A and B. The 24 bytes
per channel correspond to the channel status block defined in
the AES-3 and IEC-60958 specifications. Channel A and B
data are interleaved within the buffers, see Tables VII and VIII.
The AES-3 encoder internally accesses the TA buffer to
obtain the channel status data that is multiplexed into the
AES-3 data stream. The user accesses the UA buffer through
the control port in order to update the channel status data
when needed. The transfer of data from the UA buffer to the
TA buffer is managed internally by the DIT4096, but it may
be enabled or disabled by the user via a control register.
DISABLE UA TO TA BUFFER TRANSFER
Set BTD = 1
in Control Register 07
H
UPDATE THE CS DATA
Write Channel Status Data
to the UA Buffer
ENABLE UA TO TA BUFFER TRANSFER
Set BTD = 0
in Control Register 07
H
Read Register 04
H
to verify that the
BTI bit is set to 1.
The Host has verified that the Buffer
Transfer is complete, which completes the
Channel Status Data update.
Assume that the Buffer Transfer has
completed and that the Channel Status
data has been updated.
Is the
Buffer Transfer Interrupt (BTI)
Masked?
Is the
INT output LOW?
YES
YES
NO
NO
FIGURE 9. Flowchart for Updating the Channel Status Buffer.
bit 7 (MSB) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (LSB)
0000000BTD
Register 07
H
: Channel Status Buffer Control Register