Datasheet

DIT4096
16
SBOS225A
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whichever is the first frame to occur after the BTD bit is reset
to 0. Once the UA to TA buffer transfer is completed, the buffer
transfer interrupt (BTI) will occur, as long as it is unmasked.
The transmitter will ignore any attempt to access the UA
buffer during a UA to TA buffer transfer. In addition, the BTD
bit may be set to 1 to stop a UA to TA buffer transfer that may
be in progress, if so desired.
CHANNEL STATUS BUFFER MAP
The channel status buffer is organized in accordance with the
AES-3 and IEC-60958 standards. See Table VII for the memory
map for the UA channel status data buffer for Professional mode.
Table VIII shows the memory map for the UA channel status data
buffer for Consumer mode.
ADDRESS CS BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7
(HEX) Byte MSB LSB
8 A0 PRO = 0 AUDIO COPY EMPH EMPH EMPH MODE MODE
09 B0 PRO = 0 AUDIO COPY EMPH EMPH EMPH MODE MODE
0A A1
CAT CODE CAT CODE CAT CODE CAT CODE CAT CODE CAT CODE CAT CODE L
0B B1
CAT CODE CAT CODE CAT CODE CAT CODE CAT CODE CAT CODE CAT CODE L
0C A2 SOURCE SOURCE SOURCE SOURCE CH NUM CH NUM CH NUM CH NUM
0D B2 SOURCE SOURCE SOURCE SOURCE CH NUM CH NUM CH NUM CH NUM
0E A3 f
S
f
S
f
S
f
S
CLK ACC CLK ACC reserved reserved
0F B3 f
S
f
S
f
S
f
S
CLK ACC CLK ACC reserved reserved
10 A4 reserved reserved reserved reserved reserved reserved reserved reserved
11 B4 reserved reserved reserved reserved reserved reserved reserved reserved
12 A5 reserved reserved reserved reserved reserved reserved reserved reserved
13 B5 reserved reserved reserved reserved reserved reserved reserved reserved
14 A6 reserved reserved reserved reserved reserved reserved reserved reserved
15 B6 reserved reserved reserved reserved reserved reserved reserved reserved
16 A7 reserved reserved reserved reserved reserved reserved reserved reserved
17 B7 reserved reserved reserved reserved reserved reserved reserved reserved
18 A8 reserved reserved reserved reserved reserved reserved reserved reserved
19 B8 reserved reserved reserved reserved reserved reserved reserved reserved
1A A9 reserved reserved reserved reserved reserved reserved reserved reserved
1B B9 reserved reserved reserved reserved reserved reserved reserved reserved
1C A10 reserved reserved reserved reserved reserved reserved reserved reserved
1D B10 reserved reserved reserved reserved reserved reserved reserved reserved
1E A11 reserved reserved reserved reserved reserved reserved reserved reserved
1F B11 reserved reserved reserved reserved reserved reserved reserved reserved
20 A12 reserved reserved reserved reserved reserved reserved reserved reserved
21 B12 reserved reserved reserved reserved reserved reserved reserved reserved
22 A13 reserved reserved reserved reserved reserved reserved reserved reserved
23 B13 reserved reserved reserved reserved reserved reserved reserved reserved
24 A14 reserved reserved reserved reserved reserved reserved reserved reserved
25 B14 reserved reserved reserved reserved reserved reserved reserved reserved
26 A15 reserved reserved reserved reserved reserved reserved reserved reserved
27 B15 reserved reserved reserved reserved reserved reserved reserved reserved
28 A16 reserved reserved reserved reserved reserved reserved reserved reserved
29 B16 reserved reserved reserved reserved reserved reserved reserved reserved
2A A17 reserved reserved reserved reserved reserved reserved reserved reserved
2B B17 reserved reserved reserved reserved reserved reserved reserved reserved
2C A18 reserved reserved reserved reserved reserved reserved reserved reserved
2D B18 reserved reserved reserved reserved reserved reserved reserved reserved
2E A19 reserved reserved reserved reserved reserved reserved reserved reserved
2F B19 reserved reserved reserved reserved reserved reserved reserved reserved
30 A20 reserved reserved reserved reserved reserved reserved reserved reserved
31 B20 reserved reserved reserved reserved reserved reserved reserved reserved
32 A21 reserved reserved reserved reserved reserved reserved reserved reserved
33 B21 reserved reserved reserved reserved reserved reserved reserved reserved
34 A22 reserved reserved reserved reserved reserved reserved reserved reserved
35 B22 reserved reserved reserved reserved reserved reserved reserved reserved
36 A23 reserved reserved reserved reserved reserved reserved reserved reserved
37 B23 reserved reserved reserved reserved reserved reserved reserved reserved
TABLE VIII. Channel Status Buffer for Consumer Mode (PRO = 0).
INTERRUPT SOURCES
(SOFTWARE MODE ONLY)
The DIT4096 can be programmed to generate interrupts for
up to three predefined conditions. The interrupt output, INT
(pin 22), is set low when a valid interrupt occurs. The interrupt
status register, 04
H
, is then read to determine the source of
the interrupt. Status register bits and the INT
output pin
remain active until the status register is read. Once read,
status bits are cleared and the INT
pin is pulled high by an
external pull-up resistor to V
IO
.
Interrupts may be masked using control register 05
H
. When
masked, the interrupt mechanism associated with a particular
status bit is disabled.