DIX 419 2 DIX4192 SBFS031C – JANUARY 2006 – REVISED JUNE 2006 Integrated Digital Audio Interface Receiver and Transmitter FEATURES • • • Digital Audio Interface Transmitter (DIT) – Supports Sampling Rates Up to 216kHz – Includes Differential Line Driver and CMOS Buffered Outputs – Block-Sized Data Buffers for Both Channel Status and User Data – Status Registers and Interrupt Generation for Flag and Error Conditions Digital Audio Interface Receiver (DIR) – PLL Loc
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 DESCRIPTION The DIX4192 is a highly-integrated CMOS device designed for use in professional and broadcast digital audio systems. The DIX4192 combines a digital audio interface receiver (DIR) and transmitter (DIT), two audio serial ports, and flexible distribution logic for interconnection of the function block data and clocks. The DIR and DIT are compatible with the AES3, S/PDIF, IEC 60958, and EIAJ CP-1201 interface standards.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 ELECTRICAL CHARACTERISTICS: General, DIR, and DIT All specifications are at TA = +25°C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwise noted. DIX4192 PARAMETER CONDITIONS MIN TYP MAX UNITS VIO V DIGITAL I/O CHARACTERISTICS (All I/O pins except line receivers and line driver) High-level input voltage, VIH 0.7 × VIO Low-level input voltage, VIL 0 High-level input current, IIH 0.5 0.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 ELECTRICAL CHARACTERISTICS: Audio Serial Ports All specifications are at TA = +25°C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwise noted. DIX4192 PARAMETER CONDITIONS MIN TYP MAX UNITS 216 kHz 13.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 ELECTRICAL CHARACTERISTICS: I2C Standard and Fast Modes All specifications are at TA = +25°C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwise noted. DIX4192 PARAMETER HOST INTERFACE: I2C Standard CONDITIONS MIN TYP MAX UNITS 100 kHz Mode (1) SCL clock frequency, fSCL 0 Hold time repeated START condition, tHDSTA 4 µs Low period of SCL clock, tLOW 4.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 ELECTRICAL CHARACTERISTICS: Power Supplies All specifications are at TA = +25°C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwise noted. DIX4192 PARAMETER CONDITIONS MIN TYP MAX UNITS VDD18 +1.65 +1.8 +1.95 V VDD33 +3.0 +3.3 +3.6 V VIO +1.65 +3.3 +3.6 V VCC +3.0 +3.3 +3.6 V POWER SUPPLIES Recommended supply voltage range Supply current: initial startup IDD18S VDD18 = +1.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 TIMING DIAGRAMS LRCK tBCKH BCK tAIS tBCKL SDIN tAIH tAOD SDOUT Figure 1. Audio Serial Port Timing tCFCS CS tCSCR tCDS CCLK tCDH CDIN Hi Z Hi Z CDOUT tCFDO tCSZ Figure 2. SPI Interface Timing tF SDA tLOW tSUDAT tR tHDSTA tSP tR tBUF tF SCL tHDSTA S S = Start Condition tSUSTA tHDDAT tHIGH tSUSTO R P R = Repeated Start Condition P = Stop Condition S Figure 3.
DIX4192 www.ti.
DIX4192 www.ti.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 PRODUCT OVERVIEW The DIX4192 is an integrated digital audio interface receiver and transmitter (DIR and DIT). Two audio serial ports, Port A and Port B, support input and output interfacing to external data converters, signal processors, and logic devices. On-chip routing logic provides for flexible interconnection between the four functional blocks. The audio serial ports and DIT may be operated at sampling rates up to 216kHz.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 PRODUCT OVERVIEW (continued) Figure 4 shows a simplified functional block diagram for the DIX4192. Additional details for each function block will be covered in respective sections of this datasheet.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 PRODUCT OVERVIEW (continued) Write or Read via 2 SPI or I C 1 RST 0 500ns (min) 500ms (min) Figure 5. Reset Sequence Timing MASTER AND REFERENCE CLOCKS The DIX4192 includes two clock inputs, MCLK (pin 25) and RXCKI (pin 13). The MCLK clock input is typically used as the master clock source for the audio serial ports and/or the DIT. The MCLK may also be utilized as the reference clock for the DIR.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 PRODUCT OVERVIEW (continued) AUDIO SERIAL PORT OPERATION The DIX4192 includes two audio serial ports, Port A and Port B. Both ports are 4-wire synchronous serial interfaces, supporting simultaneous input and output operation. Since each port has only one pair of left/right word and bit clocks, the input and output sampling rates are identical. A simplified block diagram is shown in Figure 6.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 PRODUCT OVERVIEW (continued) Channel 1 (Left Channel) Channel 2 (Right Channel) LRCKA LRCKB BCKA BCKB Audio Data MSB LSB MSB LSB (a) Left-Justified Data Format LRCKA LRCKB BCKA BCKB Audio MSB Data LSB MSB LSB (b) Right-Justified Data Format LRCKA LRCKB BCKA BCKB Audio Data MSB LSB MSB LSB 2 (c) I S Data Format 1/fs Figure 7.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 PRODUCT OVERVIEW (continued) For AES3 transmission, data is encoded into frames, with each frame containing two subframes of audio and status data, corresponding to audio Channels 1 and 2 (or Left and Right, respectively, for stereophonic audio). Figure 8 shows the AES3 frame and subframe formatting.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 PRODUCT OVERVIEW (continued) The binary non-return to zero (NRZ) formatted audio and status source data for bits 4 through 31 of each subframe are encoded utilizing a Biphase Mark format for transmission. This format allows for clock recovery at the receiver end, as well as making the interface insensitive to the polarity of the balanced cable connections.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 PRODUCT OVERVIEW (continued) The Parity (P) bit will always be generated by the AES3 encoder internal parity generator logic, such that bits 4 through 31 of the AES3-encoded subframe are even parity. The AES3 encoder output is connected to the output line driver and CMOS buffer source multiplexers.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 PRODUCT OVERVIEW (continued) Block Start (Frame 0 starts here) SYNC BLS (input) BLS (output) Figure 11. DIT Block Start Timing DIGITAL INTERFACE RECEIVER (DIR) OPERATION The DIR performs AES3 decoding and clock recovery and provides the differential line receiver functions. The lock range of the DIR includes frame/sampling rates from 20kHz to 216kHz. Figure 12 shows the functional block diagram for the DIR.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 PRODUCT OVERVIEW (continued) VDD33 24kW 24kW 3kW RX+ To Receiver Input and Bypass Multiplexers RX3kW 24kW 24kW DGND2 Figure 13. Differential Line Receiver Circuit The outputs of the four line receivers are connected to two 1-of-4 data selectors: the receiver input multiplexer and the bypass multiplexer.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 PRODUCT OVERVIEW (continued) The DIR includes a dedicated, active low AES3 decoder and PLL2 lock output, named LOCK (pin 11). The lock output is active only when both the AES3 decoder and PLL2 indicate a lock condition. Additional DIR status flags may be output at the general-purpose output (GPO) pins, or accessed through the status registers via the SPI or I2C host interface.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 PRODUCT OVERVIEW (continued) GENERAL-PURPOSE DIGITAL OUTPUTS The DIX4192 includes four general-purpose digital outputs, GPO1 through GPO4 (pins 26 through 29, respectively). A GPO pin may be programmed to a static high or low state. Alternatively, a GPO pin may be connected to one of 13 internal logic nodes, allowing the GPO pin to inherit the function of the selected signal.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 The SPI port supports write and read operations for multiple sequential register addresses through the implementation of an auto-increment mode. As shown in Figure 17, the auto-increment mode is invoked by simply holding the CS input low for multiple data bytes. The register address is automatically incremented after each data byte transferred, starting with the address specified by the command byte.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 Figure 20 illustrates the protocol for Standard and Fast mode Read operations. The current address read operation of Figure 20(a) assumes the value of the register address from the previously executed write or read operation, and is useful for polling a register address for status changes. Figure 20(b) and Figure 20(c) illustrate read operations for one or more random register addresses, with or without auto-increment mode enabled.
DIX4192 www.ti.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 APPLICATIONS INFORMATION Typical application diagrams and power-supply connections are presented in this section to aid the customer in hardware designs employing the DIX4192 device. Figure 22 illustrates typical application connections for the DIX4192 using an SPI host interface. The SPI host will typically be a microcontroller, digital signal processor, or a programmable logic device.
DIX4192 www.ti.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 APPLICATIONS INFORMATION (continued) +3.3V 10mF + 44 R 0.1mF 43 42 DIX4192IPFB 33 9 10mF + 0.1mF 0.1mF 10 + 10mF 30 Connect pin 44 to pin 10. Pin 10 is then connected to the ground plane. +3.3V TPS79318DBVR 1 IN 3 EN 0.1mF GND 2 OUT NR 16 17 0.1mF 5 4 C 0.01mF 2.2mF + +1.8V Optional Regulator Circuit R may be set from 2W to 10W, or replaced by a ferrite bead.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 APPLICATIONS INFORMATION (continued) RECEIVER INPUT INTERFACING This section details the recommended interfaces for the DIX4192 line receiver inputs. Balanced and unbalanced line interfaces, in addition to optical receiver and external logic interfacing, are discussed. For professional digital audio interfaces, 110Ω balanced line interfaces are either required or preferred.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 APPLICATIONS INFORMATION (continued) Optical interfaces utilizing all-plastic fiber are commonly employed for consumer audio equipment where interconnections are less than 10m in length. Optical receiver modules utilized for a digital audio interface operate from either a single +3.3V or +5V supply and have a TTL-, CMOS-, or low-voltage CMOS-compatible logic output. Interfacing to +3.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 APPLICATIONS INFORMATION (continued) The DIX4192 line receivers may also be driven directly from external logic or line receiver devices with TTL or CMOS outputs. If the logic driving the line receiver is operated from +3.3V, then logic level translation will not be required.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 APPLICATIONS INFORMATION (continued) 0.1mF 1:1 R1 TX+ Digital Output 75W Unbalanced (RCA or BNC connector) R2 (a) Transformer-Coupled Unbalanced Output 0.1mF R1 TX+ Digital Output 75W Unbalanced (RCA or BNC connector) R2 (b) Unbalanced Output Without Transformer R1 and R2 are selected to achieve the desired output voltage level while maintaining the required 75W transmitter output impedance. The TX+ output impedance is negligible.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 APPLICATIONS INFORMATION (continued) Direct to external logic operating from the VIO supply. AESOUT +5V 5 2 4 3 To +5V Logic (VIO supply = +3.0V to +3.3V) 1 SN74AHCT1G125 or Equivalent Figure 33. CMOS/TTL Output Logic Interface +5V SN75ALS191 1 8 2 AESOUT 7 VIO +3.3V 1 5 6 3 6 If VIO < +3.0V. 3 4 5 SN74AVC1T45 or Equivalent To Balanced or Unbalanced Line Interface To Balanced or Unbalanced Line Interface 2 1 Figure 34.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 Register Page 2 contains the digital interface transmitter (or DIT) channel status and user data buffers. These buffers correspond to the data contained in the C and U bits of the transmitted AES3-encoded data stream. The contents of these buffers may be written through the SPI or I2C serial host interface to configure the C and U bits of the transmitted AES3 data stream. The buffers may also be read for verification by the host system.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 CONTROL REGISTERS See Table 3 for the control and status register map of the DIX4192. Register addresses 0x00 and 0x2D through 0x7E are reserved for factory or future use. All register addresses are expressed as hexadecimal numbers. The following pages provide detailed descriptions for each control and status register. Table 3.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 Register 01: Power-Down and Reset Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) RESET 0 PDALL PDPA PDPB PDTX PDRX 0 PDRX Power-Down for the Receiver Function Block This bit is utilized to power-down the DIR and associated functions. All receiver outputs are forced low.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 Register 03: Port A Control Register 1 Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) 0 AMUTE AOUTS1 AOUTS0 AM/S AFMT2 AFMT1 AFMT0 AFMT[2:0] Port A Audio Data Format These bits are used to set the audio input and output data format for Port A. Refer to the Audio Serial Port Operation section for illustrations of the supported data formats.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 ACLK[1:0] Port A Master Clock Source These bits are used to set the master clock source for Port A when configured for Master mode operation.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 Register 06: Port B Control Register 2 Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) 0 0 0 0 BCLK1 BCLK0 BDIV1 BDIV0 BDIV[1:0] Port B Master Mode Clock Divider These bits are used to set the master clock divider for generating the LRCKB clock for Port B when configured for Master mode operation. BCKB is always set to 64 times the LRCKB clock rate in Master mode.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 TXDIV[1:0] Transmitter Master Clock Divider These bits are used to select the Transmitter master clock divider, which determines the output frame rate. TXCLK TXDIV1 TXDIV0 0 0 Clock Divider Divide the master clock by 128. (default) 0 1 Divide the master clock by 256. 1 0 Divide the master clock by 384. 1 1 Divide the master clock by 512.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 BYPMUX[1:0] Bypass Multiplexer Source Selection These bits select the line receiver output to be utilized as the bypass multiplexer data source.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 Register 0C: DIT Interrupt Mode Register Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) 0 0 0 0 TSLIPM1 TSLIPM0 TBTIM1 TBTIM0 TBTIM[1:0] Transmitter Buffer Transfer Interrupt Mode These bits are utilized to select the active trigger state for the BTI interrupt.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 Register 0E: Receiver Control Register 2 Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) 0 0 0 LOL RXAMLL RXCKOD1 RXCKOD0 RXCKOE RXCKOE RXCKOE Output Enable This bit is used to enable or disable the recovered clock output, RXCKO (pin 12). When disabled, the output is set to a high-impedance state. RXCKOE RXCKOD[1:0] RXCKO Output State 0 Disabled; the RXCKO output is set to high-impedance.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 Register 11: Receiver PLL1 Configuration Register 3 Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) D7 D6 D5 D4 D3 D2 D1 D0 Registers 0x0F through 0x11 are utilized to program PLL1 in the DIR core. PLL1 multiplies the DIR reference clock source to an oversampling rate which is adequate for AES3 decoder operation. PLL1 is programmed using the following relationship: (CLOCK × K) / P = 98.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 Register 13: Receiver Status Register 1 (Read-Only) Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) 0 0 0 0 0 0 RXCKR1 RXCKR0 RXCKR[1:0] Maximum Available Recovered Clock Rate These two bits indicate the maximum available RXCKO clock rate based upon the DIR detection circuitry, which determines the frame rate of the incoming AES3-encoded bit stream.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 1 Buffer transfer completed Register 15: Receiver Status Register 3 (Read-Only) Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) 0 0 0 0 0 0 0 OSLIP Note: Status bits must be unmasked in control register 0x17 in order for the status interrupts to be generated.
DIX4192 www.ti.
DIX4192 www.ti.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 Register 1B: General-Purpose Output 1 (GPO1) Control Register Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) 0 0 0 0 GPO13 GPO12 GPO11 GPO10 GPO[13:10] General-Purpose Output 1 (GPO1) Configuration These bits are used to set the state or data source for the general-purpose digital output pin GPO1.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 Register 1D: General-Purpose Output 3 (GPO3) Control Register Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) 0 0 0 0 GPO33 GPO32 GPO31 GPO30 GPO[33:30] General-Purpose Output 3 (GPO3) Configuration These bits are used to set the state or data source for the general-purpose digital output pin GPO3.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 Registers 1F through 28: Q-Channel Sub-Code Data Registers Registers 0x1F through 0x28 comprise the Q-channel sub-code buffer, which may be accessed for audio CD playback. The Q-channel data provides information regarding the playback status for the current disc. The buffer data is decoded by the DIR block.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 Registers 29 through 2C: IEC61937 PC/PD Burst Preamble The PC and PD burst preambles are part of the IEC61937 standard for transmission of data reduced, non-PCM audio over a standard two-channel interface (IEC60958). Examples of data-reduced formats include Dolby AC-3, DTS, various flavors of MPEG audio (including AAC), and Sony ATRAC. The PA and PB preambles provide synchronization data, and are fixed values of 0xF872 and 0x4E1F, respectively.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 Register 7F: Page Selection Register Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) 0 0 0 0 0 0 PAGE1 PAGE0 PAGE[1:0] Page Selection These bits are utilized to select one of three register pages for write and/or read access via the SPI or I2C serial host interface. The Page Selection Register is present on every register page at address 0x7F, allowing movement between pages as necessary.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 CHANNEL STATUS AND USER DATA BUFFER MAPS (continued) Table 5.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 Table 6.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 Table 7.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 Table 8.
DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 REFERENCE DOCUMENTS Throughout this data sheet, various standards and documents are repeatedly cited as references. Sources for these documents are listed here so that the reader may obtain the documents for further study. Audio Engineering Society (AES) standards documents, including the AES3, AES11, AES18, and related specifications are available from the AES web site: http://www.aes.org.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device DIX4192IPFBR Package Package Pins Type Drawing TQFP PFB 48 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 16.4 Pack Materials-Page 1 9.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 9.6 1.5 12.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DIX4192IPFBR TQFP PFB 48 1000 367.0 367.0 38.
MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°– 7° 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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