DDR2 Memory Controller User's Guide

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3.2.3 Configuring SDRAM Timing Registers (SDTIM1 and SDTIM2)
Using the DDR2 Memory Controller
Table 12 displays the DDR2-533 refresh rate specification.
Table 12. DDR2 Memory Refresh Specification
Symbol Description Value
t
REF
Average Periodic Refresh Interval 7.8 μ s
Therefore, the value for the REFRESH-RATE can be calculated as follows:
REFRESH_RATE = 266.5 MHz × 7.8 μ s = 2078.7 = 81Eh
Table 13 shows the resulting SDRFC configuration.
Table 13. SDRFC Configuration
Field Value Function Selection
SR 0 DDR2 memory controller is not in self-refresh mode.
REFRESH_RATE 81Eh Set to 81Eh DDR2 clock cycles to meet the DDR2 memory refresh rate
requirement.
The SDRAM timing 1 register (SDTIM1) and SDRAM timing 2 register (SDTIM2) configure the DDR2
memory controller to meet the data sheet timing parameters of the attached DDR2 device. Each field in
SDTIM1 and SDTIM2 corresponds to a timing parameter in the DDR2 data sheet specification. Table 14
and Table 15 display the register field name and corresponding DDR2 data sheet parameter name along
with the data sheet value. These tables also provide a formula to calculate the register field value and
displays the resulting calculation. Each of the equations include a minus 1 because the register fields are
defined in terms of DDR2 clock cycles minus 1. See Section 4.5 and Section 4.6 for more information.
Table 14. SDTIM1 Configuration
DDR2 SDRAM
Data Sheet
Register Parameter Data Sheet Formula (Register Field Field
Field Name Name Description Value (nS) Must Be ≥ ) Value
T_RFC t
RFC
Refresh cycle time 127.5 (t
RFC
× f
DDR2_CLK
) - 1 33
T_RP t
RP
Precharge command to refresh or 15 (t
RP
× f
DDR2_CLK
) - 1 3
activate command
T_RCD t
RCD
Activate command to read/write 15 (t
RCD
× f
DDR2_CLK
) - 1 3
command
T_WR t
WR
Write recovery time 15 (t
WR
× f
DDR2_CLK
) - 1 3
T_RAS t
RAS
Active to precharge command 40 (t
RAC
× f
DDR2_CLK
) - 1 10
T_RC t
RC
Activate to Activate command in the 55 (t
RC
× f
DDR2_CLK
) - 1 14
same bank
T_RRD t
RRD
Activate to Activate command in a 10 (t
RRD
× f
DDR2_CLK
) - 1 3
different bank
T_WTR t
WTR
Write to read command delay 7.5 (t
WTR
× f
DDR2_CLK
) - 1 1
DSP DDR2 Memory Controller34 SPRUEK5A – October 2007
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