DDR2 Memory Controller User's Guide

List of Tables
1 DDR2 Memory Controller Signal Descriptions ......................................................................... 12
2 DDR2 SDRAM Commands ............................................................................................... 13
3 Truth Table for DDR2 SDRAM Commands ............................................................................ 13
4 Addressable Memory Ranges ............................................................................................ 18
5 Bank Configuration Register Fields for Address Mapping ............................................................ 19
6 DDR2 Memory Controller FIFO Description ............................................................................ 22
7 Refresh Urgency Levels ................................................................................................... 25
8 Reset Sources .............................................................................................................. 26
9 DDR2 SDRAM Mode Register Configuration ........................................................................... 27
10 DDR2 SDRAM Extended Mode Register 1 Configuration ............................................................ 27
11 SDCFG Configuration ..................................................................................................... 33
12 DDR2 Memory Refresh Specification ................................................................................... 34
13 SDRFC Configuration ...................................................................................................... 34
14 SDTIM1 Configuration ..................................................................................................... 34
15 SDTIM2 Configuration ..................................................................................................... 35
16 DMCCTL Configuration .................................................................................................... 35
17 DDR2 Memory Controller Registers ..................................................................................... 36
18 Module ID and Revision Register (MIDR) Field Descriptions ........................................................ 37
19 DDR2 Memory Controller Status Register (DMCSTAT) Field Descriptions ........................................ 37
20 SDRAM Configuration Register (SDCFG) Field Descriptions ........................................................ 38
21 SDRAM Refresh Control Register (SDRFC) Field Descriptions ..................................................... 40
22 SDRAM Timing 1 Register (SDTIM1) Field Descriptions ............................................................. 41
23 SDRAM Timing 2 Register (SDTIM2) Field Descriptions ............................................................. 43
24 Burst Priority Register (BPRIO) Field Descriptions .................................................................... 44
25 DDR2 Memory Controller Control Register (DMCCTL) Field Descriptions ......................................... 45
A-1 Document Revision History ............................................................................................... 46
SPRUEK5A – October 2007 List of Tables 5
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