Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - transceivers MII, RMII 1/1 LLP 48 EP

DP83620

www.ti.com

SNLS339C –JANUARY 2011–REVISED APRIL 2013

DP83620 Industrial Temperature Single Port 10/100 Mbps Ethernet Physical Layer

Transceiver with Fiber Support (FX)

Check for Samples: DP83620

1 Introduction

1.1 Features

• Deterministic, Low Transmit and Receive • RMII Rev. 1.2 and MII MAC Interface

Latency

• RMII Master Mode

• Selectable Frequency Synchronized Clock

• Synchronous Ethernet

Output

• 25 MHz MDC and MDIO Serial Management

• Dynamic Link Quality Monitoring

Interface

• TDR Based Cable Diagnostic and Cable Length

• IEEE 802.3u 100BASE-FX Fiber Interface

Detection

• IEEE 1149.1 JTAG

• 10/100 Mb/s Packet BIST (Built in Self Test)

• Programmable LED Support for Link, 10 /100

• Error-Free Operation up to 150 Meters CAT5

Mb/s Mode, Duplex, Activity, and Collision

Cable

Detect

• ESD Protection - 8 kV Human Body Model

• Optional 100BASE-TX Fast Link Loss Detection

• 2.5 V and 3.3 V I/Os and MAC Interface

• Industrial Temperature Range

• Auto-MDIX for 10/100 Mbps

• 48 Pin WQFN Package (7mm) x (7mm)

• Auto-Crossover in Forced Modes of Operation

1.2 Applications

• Factory Automation

• General Embedded Applications

1.3 Description

The DP83620 is a highly reliable, feature rich device suited for industrial applications. The DP83620 offers

low power consumption, including several intelligent power down states. In addition to low power, the

DP83620 is optimized for cable length performance far exceeding IEEE specifications. The DP83620

includes a 25MHz clock out. This allows the application to be designed with a minimum of external parts,

which in turn results in the lowest possible total cost of the solution.

The DP83620 offers innovative diagnostic features unique to Texas Instruments, including dynamic

monitoring of link quality during standard operation for fault prediction. These advanced features allow the

system designer to implement a fault prediction mechanism to detect and warn of deteriorating and

changing link conditions. This single port fast Ethernet transceiver can support both copper and fiber

media. The DP838620 also provides flexibility by supporting both MII and RMII interfaces.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to

specifications per the terms of the Texas Instruments standard warranty. Production

processing does not necessarily include testing of all parameters.

Summary of content (105 pages)

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DP83620 www.ti.com SNLS339C – JANUARY 2011 – REVISED APRIL 2013 DP83620 Industrial Temperature Single Port 10/100 Mbps Ethernet Physical Layer Transceiver with Fiber Support (FX) Check for Samples: DP83620 1 Introduction 1.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 1 .............................................. 1 ............................................. 1 1.2 Applications .......................................... 1 1.3 Description ........................................... 1 Device Information ...................................... 4 2.1 System Diagram ..................................... 4 2.2 Block Diagram ....................................... 4 Pin Descriptions ......................................
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DP83620 www.ti.com 10 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 .......................... ....................... 9.3 ESD PROTECTION ................................ 9.4 CLOCK IN (X1) RECOMMENDATIONS ........... Register Block ......................................... 10.1 REGISTER DEFINITION ........................... ............... ...................... LINK DIAGNOSTICS REGISTERS - PAGE 2 ...... 9.1 TPI NETWORK CIRCUIT 62 10.2 EXTENDED REGISTERS - PAGE 0 80 9.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com 2 Device Information MPU/CPU MII or RMII RJ45 DP83620 10/100 Mb/s PHYTER 10BASE-T 100BASE-TX or Fiber Transceiver 100BASE-FX Status LEDs Clock 2.2 Magnetics System Diagram Media Access Control (MAC) 2.
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DP83620 www.ti.com SNLS339C – JANUARY 2011 – REVISED APRIL 2013 3 Pin Descriptions The DP83620 pins are classified into the following interface categories (each interface is described in the sections that follow): • Serial Management Interface • MAC Data Interface • Clock Interface • LED Interface • JTAG Interface • Reset and Power Down • Strap Options • 10/100 Mb/s PMD Interface • Power and Ground pins NOTE Strapping pin option. Please see Section 3.9 for strap definitions.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 IO_VSS RXD_0 RXD_1 RXD_2 RXD_3 COL RX_ER CRS/CRS_DV RX_DV RX_CLK RESERVED Pin Layout IO_VDD 3.1 www.ti.
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DP83620 www.ti.com 3.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 3.3 www.ti.com SERIAL MANAGEMENT INTERFACE Signal Name Pin Name Type Pin # Description MDC MDC I 31 MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO management data input/output serial interface which may be asynchronous to transmit and receive clocks. The maximum clock rate is 25 MHz with no minimum clock rate.
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DP83620 www.ti.com SNLS339C – JANUARY 2011 – REVISED APRIL 2013 Type Pin # Description CRS/CRS_DV Signal Name CRS/CRS_DV S, O, PU 40 MII CARRIER SENSE: Asserted high to indicate the receive medium is non-idle. RMII CARRIER SENSE/RECEIVE DATA VALID: This signal combines the RMII Carrier and Receive Data Valid indications. For a detailed description of this signal, see the RMII Specification.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 3.7 www.ti.com JTAG INTERFACE Signal Name Pin Name Type Pin # Description TCK TCK I, PU 8 TEST CLOCK TDO TDO O 9 TEST OUTPUT TMS TMS I, PU 10 TEST MODE SELECT TRST# TRST# I, PU 11 This pin has a weak internal pullup. This pin has a weak internal pullup. TEST RESET: Active low test reset. This pin has a weak internal pullup. TDI TDI I, PU 12 TEST DATA INPUT This pin has a weak internal pullup. 3.
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DP83620 www.ti.com Signal Name AN_EN AN1 AN0 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 Pin Name LED_LINK LED_SPEED/FX_S D LED_ACT Type Pin # Description S, O, PU S, O, PU 28 27 S, O, PU 26 AUTO-NEGOTIATION ENABLE: When high, this enables AutoNegotiation with the capability set by AN0 and AN1 pins. When low, this puts the part into Forced Mode with the capability set by AN0 and AN1 pins.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com 3.10 10 Mb/s AND 100 Mb/s PMD INTERFACE Signal Name Pin Name Type Pin # Description TDTD+ TDTD+ I/O 16 17 Differential common driver transmit output (PMD Output Pair). These differential outputs are automatically configured to either 10BASE-T or 100BASE-TX signaling. In Auto-MDIX mode of operation, this pair can be used as the Receive Input pair. In 100BASE-FX mode, this pair becomes the 100BASE-FX Transmit pair.
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DP83620 www.ti.com SNLS339C – JANUARY 2011 – REVISED APRIL 2013 4 Electrical Specifications 4.1 Absolute Maximum Ratings (1) (2) (3) Supply Voltage (VCC) -0.5 V to 4.2 V DC Input Voltage (VIN) -0.5V to VCC + 0.5V DC Output Voltage (VOUT) -0.5V to VCC + 0.5V Storage Temperature (TSTG ) -65°C to 150°C Maximum Case Temperature for TA = 85 °C 95 °C Maximum Die Temperature (Tj) ESD Rating (1) (2) (3) 4.2 150 °C (RZAP = 1.5k, CZAP = 120 pF) 8.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 4.4 www.ti.com DC Specifications Symbol Pin Types Parameter VIH I I/O Input High Voltage VIL I I/O Input Low Voltage IIH I I/O IIL Conditions Min Typ Max 2.0 Units V VI/O = 3.3 V 0.8 V VI/O = 2.5 V 0.7 V Input High Current VIN = VI/O 10 µA I I/O Input Low Current VIN = GND 10 µA VOL O I/O Output Low Voltage IOL = 4 mA 0.4 V VOH O I/O Output High Voltage IOH = -4 mA VI/O - 0.
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DP83620 www.ti.com 4.5 AC Specifications — Power Up Timing Parameter T2.1.1 T2.1.2 T2.1.3 (1) SNLS339C – JANUARY 2011 – REVISED APRIL 2013 Notes Min Post Power Up Stabilization time prior to MDC preamble for register accesses (1) Description Typ MDIO is pulled high for 32-bit serial management initialization. 167 ms Hardware Configuration Latch-in Time from power up (1) Hardware Configuration Pins are described in the Pin Description section.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 4.6 www.ti.com AC Specifications — Reset Timing Parameter Description Notes Min Typ Max Units T2.2.1 Post RESET Stabilization time prior to MDC preamble for register accesses MDIO is pulled high for 32-bit serial management initialization 3 µs T2.2.2 Hardware Configuration Latch-in Time from the Deassertion of RESET (either soft or hard) (1) Hardware Configuration Pins are described in the Pin Description section 3 µs 50 ns T2.2.
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DP83620 www.ti.com 4.7 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 AC Specifications — MII Serial Management Timing Parameter Description Notes Min T2.3.1 MDC to MDIO (Output) Delay Time 0 T2.3.2 MDIO (Input) to MDC Setup Time 10 T2.3.3 MDIO (Input) to MDC Hold Time 10 T2.3.4 MDC Frequency Typ Max Units 20 ns ns ns 2.5 25 MHz MDC T2.3.4 T2.3.1 MDIO (output) MDC T2.3.2 Valid Data MDIO (input) 4.8 T2.3.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com 4.10 AC Specifications — 100BASE-TX and 100BASE-FX MII Transmit Packet Latency Timing Parameter T2.6.
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DP83620 www.ti.com SNLS339C – JANUARY 2011 – REVISED APRIL 2013 4.12 AC Specifications — 100BASE-TX Transmit Timing (tR/F & Jitter) Parameter T2.8.1 Description 100 Mb/s tR and tF Mismatch T2.8.2 (1) (2) Notes Min Typ Max Units 3 4 5 ns 500 ps 1.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com 4.14 AC Specifications — 100BASE-TX and 100BASE-FX MII Receive Packet Deassertion Timing Parameter T2.10.1 (1) (2) Description Notes Carrier Sense OFF Delay (1) (2) Min Typ 100BASE-TX mode 24 100BASE-FX mode 14 Max Units bits Carrier Sense Off Delay is determined by measuring the time from the first bit of the “T” code group to the deassertion of Carrier Sense. 1 bit time = 10 ns in 100 Mb/s mode.
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DP83620 www.ti.com SNLS339C – JANUARY 2011 – REVISED APRIL 2013 4.17 AC Specifications — 10BASE-T MII Transmit Timing (Start of Packet) Parameter T2.13.1 (1) Description Notes Transmit Output Delay from the Falling Edge of TX_CLK (1) Min 10 Mb/s MII mode Typ Max Units 3.5 bits 1 bit time = 100 ns in 10 Mb/s. TX_CLK TX_EN TXD[3:0] PMD Output Pair T2.13.1 4.18 AC Specifications — 10BASE-T MII Transmit Timing (End of Packet) Min Typ T2.14.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com 4.19 AC Specifications — 10BASE-T MII Receive Timing (Start of Packet) Parameter T2.15.1 Description Min Typ Max Units 630 1000 ns (1) (2) T2.15.2 RX_DV Latency T2.15.
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DP83620 www.ti.com SNLS339C – JANUARY 2011 – REVISED APRIL 2013 4.22 AC Specifications — 10 Mb/s Jabber Timing Parameter Description Notes Min Typ Max Units T2.18.1 Jabber Activation Time 85 ms T2.18.2 Jabber Deactivation Time 500 ms TX_EN T2.18.1 T2.18.2 PMD Output Pair COL 4.23 AC Specifications — 10BASE-T Normal Link Pulse Timing Parameter Description Notes Min Typ (1) Max Units T2.19.1 Pulse Width 100 ns T2.19.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com 4.25 AC Specifications — 100BASE-TX Signal Detect Timing Parameter T2.21.1 Description Min (1) T2.21.2 SD Internal Turn-off Time (1) (2) Notes Typ SD Internal Turn-on Time Default operation Fast link-loss indication enabled (2) 250 1.3 Max Units 1 ms 300 µs µs The signal amplitude on PMD Input Pair must be TP-PMD compliant. Fast Link-loss detect is enabled by setting the SD_CNFG[8] register bit to a 1. PMD Input Pair T2.21.
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DP83620 www.ti.com SNLS339C – JANUARY 2011 – REVISED APRIL 2013 4.27 AC Specifications — 10 Mb/s Internal Loopback Timing Parameter T2.23.1 (1) Description TX_EN to RX_DV Loopback (1) Notes Min Typ 10 Mb/s internal loopback mode Max Units 2 µs Measurement is made from the first falling edge of TX_CLK after assertion of TX_EN. TX_CLK TX_EN TXD[3:0] CRS/CRS_DV T2.23.1 RX_CLK RX_DV RXD[3:0] 4.28 AC Specifications — RMII Transmit Timing (Slave Mode) Parameter Description Notes T2.24.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com 4.29 AC Specifications — Transmit Timing (Master Mode) Parameter Description Notes Min 20 Max Units RX_CLK, TX_CLK, CLK_OUT Period T2.25.2 TXD[1:0], TX_EN Data Setup to RX_CLK, TX_CLK, CLK_OUT rising edge 4 ns T2.25.3 TXD[1:0], TX_EN Data Hold from RX_CLK, TX_CLK, CLK_OUT rising edge 2 ns T2.25.
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DP83620 www.ti.com SNLS339C – JANUARY 2011 – REVISED APRIL 2013 4.30 AC Specifications — RMII Receive Timing (Slave Mode) Parameter Description Notes T2.26.1 X1 Clock Period T2.26.2 RXD[1:0], CRS_DV, and RX_ER output delay from X1 rising edge (1) T2.26.3 T2.26.4 T2.26.5 (1) (2) (3) (4) (5) (6) Min Typ 50 MHz Reference Clock CRS ON delay (2) (3) CRS OFF delay (4) RXD[1:0] and RX_ER latency (5) (6) Max Units 20 2 ns 14 100BASE-TX mode 18.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com 4.31 AC Specifications — RMII Receive Timing (Master Mode) Parameter Description Notes T2.27.1 RX_CLK, TX_CLK, CLK_OUT Clock Period T2.27.2 RXD[1:0], CRS_DV, RX_DV and RX_ER output delay from RX_CLK, TX_CLK, CLK_OUT rising edge (1) T2.27.3 T2.27.4 T2.27.5 (1) (2) (3) (4) (5) CRS ON delay (2) (3) CRS OFF delay (4) RXD[1:0] and RX_ER latency (5) Min Typ 50 MHz Reference Clock Max 20 2 ns 14 100BASE-TX mode 18.
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DP83620 www.ti.com SNLS339C – JANUARY 2011 – REVISED APRIL 2013 4.33 AC Specifications — CLK_OUT Timing (RMII Slave Mode) Parameter Description T2.29.1 CLK_OUT High/Low Time T2.29.2 CLK_OUT propagation delay Notes Min Typ Max Units 10 ns Relative to X1 8 ns Max Units X1 T2.29.2 T2.29.1 T2.29.1 CLK_OUT 4.34 AC Specifications — Single Clock MII (SCMII) Transmit Timing Parameter Description Notes Min Typ T2.30.1 X1 Clock Period 25 MHz Reference Clock T2.30.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com 4.35 AC Specifications — Single Clock MII (SCMII) Receive Timing Parameter Description Notes Min T2.31.1 X1 Clock Period 25 MHz Reference Clock T2.31.2 RXD[3:0], RX_DV and RX_ER output delay (1) From X1 rising edge T2.31.3 T2.31.4 T2.31.
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DP83620 www.ti.com SNLS339C – JANUARY 2011 – REVISED APRIL 2013 5 Configuration This section includes information on the various configuration options available with the DP83620. The configuration options described below include: — Media Configuration — Auto-Negotiation — PHY Address and LEDs — Half Duplex vs. Full Duplex — Isolate mode — Loopback mode — BIST 5.1 MEDIA CONFIGURATION The DP83620 supports both Twister Pair (100BASE-TX and 10BASE-T) and Fiber (100BASE-FX) media.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com Table 5-1. Auto-Negotiation Modes 5.2.
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DP83620 www.ti.com SNLS339C – JANUARY 2011 – REVISED APRIL 2013 The Auto-Negotiation Expansion Register (ANER) indicates additional Auto-Negotiation status.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 5.3 www.ti.com AUTO-MDIX When enabled, this function utilizes Auto-Negotiation to determine the proper configuration for transmission and reception of data and subsequently selects the appropriate MDI pair for MDI/MDIX operation. The function uses a random seed to control switching of the crossover circuitry. This implementation complies with the corresponding IEEE 802.3 Auto-Negotiation and Crossover Specifications.
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DP83620 www.ti.com SNLS339C – JANUARY 2011 – REVISED APRIL 2013 Since the PHYAD[0] pin has weak internal pull-up resistor and PHYAD[4:1] pins have weak internal pulldown resistors, the default setting for the PHY address is 00001 (01h). PHYAD4 = 0 PHYAD3 = 0 PHYAD2 = 0 COL RXD_3 RXD_2 RXD_0 RXD_1 Refer to Figure 5-1 for an example of a PHYAD connection to external components. In this example, the PHYAD strapping results in address 00011 (03h). PHYAD1 = 1 PHYAD0 = 1 2.2 k: VCC Figure 5-1.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com Table 5-3.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 LED_ACT LED_LINK LED_SPEED www.ti.com AN1 = 1 AN0 = 1 165: 165: 165: VCC 2.2 k: AN_EN = 0 GND Figure 5-2. AN Strapping and LED Loading Example 5.6.2 LED Direct Control The DP83620 provides another option to directly control any or all LED outputs through the LED Direct Control Register (LEDCR), address 18h. The register does not provide read access to LEDs. 5.7 HALF DUPLEX vs.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 5.8 www.ti.com INTERNAL LOOPBACK The DP83620 includes a Loopback Test mode for facilitating system diagnostics. The Loopback mode is selected through bit 14 (Loopback) of the Basic Mode Control Register (BMCR). Writing 1 to this bit enables MII transmit data to be routed to the MII receive outputs. Loopback status may be checked in bit 3 of the PHY Status Register (PHYSTS). While in Loopback mode the data will not be transmitted onto the media.
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DP83620 www.ti.com SNLS339C – JANUARY 2011 – REVISED APRIL 2013 5.11 LINK DIAGNOSTIC CAPABILITIES The DP83620 contains several system diagnostic capabilities for evaluating link quality and detecting potential cabling faults in twisted pair cabling. Software configuration is available through the Link Diagnostics Registers - Page 2 which can be selected via Page Select Register (PAGESEL), address 13h.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com Two different versions of the Frequency Offset may be monitored through bits [7:0] of register FREQ100 (15h). The first is the long-term Frequency Offset. The second is the current Frequency Control value, which includes short-term phase adjustments and can provide information on the amount of jitter in the system. 5.11.1.
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DP83620 www.ti.com SNLS339C – JANUARY 2011 – REVISED APRIL 2013 5.11.2.2 Checking Current Parameter Values Prior to setting Threshold values, it is recommended that software check current adapted values. The thresholds may then be set relative to the adapted values. The current adapted values can be read using the LQDR register by setting the SAMPLE_PARAM bit [13] of LQDR, address (1Eh). For example, to read the DBLW current value: 1.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com The TDR cable diagnostics works best in certain conditions. For example, an unterminated cable provides a good reflection for measuring cable length, while a cable with an ideal termination to an unpowered partner may provide no reflection at all. 5.11.4 TDR Pulse Generator The TDR implementation can send two types of TDR pulses. The first option is to send 50 ns or 100 ns link pulses from the 10 Mb Common Driver.
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DP83620 www.ti.com SNLS339C – JANUARY 2011 – REVISED APRIL 2013 5.11.7 TDR Results The results of a TDR peak and threshold measurement are available in the TDR Peak Measurement Register (TDR_PEAK), address 18h and TDR Threshold Measurement Register (TDR_THR), address 19h. The threshold measurement may be a more accurate method of measuring the length of longer cables since it provides a better indication of the start of the received pulse, rather than the peak value.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com 6 MAC Interface The DP83620 supports several modes of operation using the MII interface pins. The options are defined in the following sections and include: — MII Mode — RMII Mode — Single Clock MII Mode (SCMII) In addition, the DP83620 supports the standard 802.3u MII Serial Management Interface. The modes of operation can be selected by strap options or register control.
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DP83620 www.ti.com SNLS339C – JANUARY 2011 – REVISED APRIL 2013 When heartbeat is enabled (only applicable to 10 Mb/s operation), approximately 1µs after the transmission of each packet, a Signal Quality Error (SQE) signal of approximately 10 bit times is generated (internally) to indicate successful transmission. SQE is reported as a pulse on the COL signal of the MII. Collision is not indicated during Full Duplex operation. 6.1.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com The elasticity buffer will force Frame Check Sequence errors for packets which overrun or underrun the FIFO. Underrun and overrun conditions can be reported in the RMII and Bypass Register (RBR). Table 61 indicates how to program the elasticity buffer FIFO (in 4-bit increments) based on expected maximum packet size and clock accuracy. It assumes both clocks (RMII Reference clock and far-end Transmitter clock) have the same accuracy.
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DP83620 www.ti.com SNLS339C – JANUARY 2011 – REVISED APRIL 2013 Table 6-2. Supported SCMII Packet Sizes at +/-50 ppm Frequency Accuracy Start Threshold RBR[1:0] 6.4 6.4.1 Latency Tolerance Recommended Packet Size at +/- 50 ppm 100 Mb 10 Mb 100 Mb 10 Mb 01 (default) 4 bits 8 bits 4,000 bytes 9,600 bytes 10 4 bits 8 bits 4,000 bytes 9,600 bytes 11 8 bits 8 bits 9,600 bytes 9,600 bytes 00 8 bits 8 bits 9,600 bytes 9,600 bytes IEEE 802.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com The Start code is indicated by a <01> pattern. This assures the MDIO line transitions from the default idle line state. Turnaround is defined as an idle bit time inserted between the Register Address field and the Data field. To avoid contention during a read transaction, no device shall actively drive the MDIO signal during the first bit of Turnaround.
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DP83620 www.ti.com SNLS339C – JANUARY 2011 – REVISED APRIL 2013 The PHY Control Frame may also be used to read a register location. The read value will be returned in a PHY Status Frame if that function is enabled. Only a single read may be outstanding at any time, so only one read should be included in a single PHY Control Frame.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com 7 Architecture This section describes the operations within each transceiver module, 100BASE-TX and 10BASE-T. Each operation consists of several functional blocks and is described in the following: — 100BASE-TX Transmitter — 100BASE-TX Receiver — 100BASE-FX Operation — 10BASE-T Transceiver Module 7.
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DP83620 www.ti.com SNLS339C – JANUARY 2011 – REVISED APRIL 2013 TX_CLK DIVIDE BY 5 TXD[3:0]/ TX_EN 4B5B CODEGROUP ENCODER and INJECTOR 5B PARALLEL TO SERIAL 125 MHz CLOCK SCRAMBLER MUX BP_SCR 100BASE-TX LOOPBACK MLT[1:0] NRZ TO NRZI ENCODER BINARY TO MLT-3/ COMMON DRIVER PMD OUTPUT PAIR Figure 7-1.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com Table 7-1.
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DP83620 www.ti.com 7.1.1 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 Code-Group Encoding and Injection The code-group encoder converts 4-bit (4B) nibble data generated by the MAC into 5-bit (5B) code-groups for transmission. This conversion is required to allow control data to be combined with packet data codegroups. Refer to Table 7-1 for 4B to 5B code-group mapping details.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com The Receive section consists of the following functional blocks: — Analog Front End — Input and BLW Compensation — Signal Detect — Digital Adaptive Equalization — MLT-3 to Binary Decoder — Clock Recovery Module — NRZI to NRZ Decoder — Serial to Parallel — Descrambler (bypass option) — Code Group Alignment — 4B/5B Decoder — Link Integrity Monitor — Bad SSD Detection 7.2.
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DP83620 www.ti.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 7.2.3 www.ti.com Signal Detect The signal detect function of the DP83620 is incorporated to meet the specifications mandated by the ANSI FDDI TP-PMD Standard as well as the IEEE 802.3 100BASE-TX Standard for both voltage thresholds and timing parameters. Note that the reception of normal 10BASE-T link pulses and fast link pulses per IEEE 802.3u AutoNegotiation by the 100BASE-TX receiver do not cause the DP83620 to assert signal detect. 7.2.
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DP83620 www.ti.com 7.2.9 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 Code-Group Alignment The code-group alignment module operates on unaligned 5-bit data from the descrambler (or, if the descrambler is bypassed, directly from the NRZI/NRZ decoder) and converts it into 5B code-group data (5 bits). Code-group alignment occurs after the J/K code-group pair is detected. Once the J/K code-group pair (11000 10001) is detected, subsequent data is aligned on a fixed boundary. 7.2.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 7.3.3 www.ti.com Far-End Fault Since 100BASE-FX does not support Auto-Negotiation, a Far-End Fault facility is included which allows for detection of link failures. When no signal is being received as determined by the Signal Detect function, the device sends a FarEnd Fault indication to the far-end peer. The Far-End Fault indication is comprised of 3 or more repeating cycles, each consisting of 84 one’s followed by 1 zero.
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DP83620 www.ti.com SNLS339C – JANUARY 2011 – REVISED APRIL 2013 Valid data is considered to be present until the squelch level has not been generated for a time longer than 150 ns, indicating the End of Packet. Once good data has been detected, the squelch levels are reduced to minimize the effect of noise causing premature End of Packet detection. The receive squelch threshold level can be lowered for use in longer cable or STP applications.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 7.4.6 www.ti.com Jabber Function The jabber function monitors the DP83620's output and disables the transmitter if it attempts to transmit a packet of longer than legal size. A jabber timer monitors the transmitter and disables the transmission if the transmitter is active for approximately 85 ms. Once disabled by the Jabber function, the transmitter stays disabled for the entire time that the ENDEC module's internal transmit enable is asserted.
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DP83620 www.ti.com SNLS339C – JANUARY 2011 – REVISED APRIL 2013 8 Reset Operation The DP83620 includes an internal power-on reset (POR) function and does not need to be explicitly reset for normal operation after power up. If required during normal operation, the device can be reset by a hardware or software reset. 8.1 HARDWARE RESET A hardware reset is accomplished by applying a low pulse (TTL level), with a duration of at least 1 µs, to the RESET_N pin.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com 9 Design Guidelines 9.1 TPI NETWORK CIRCUIT Figure 9-1 shows the recommended circuit for a 10/100 Mb/s twisted pair interface. Below is a partial list of recommended transformers. It is important that the user realize that variations with PCB and component characteristics requires that the application be tested to ensure that the circuit meets the requirements of the intended application.
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DP83620 www.ti.com 9.2 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 FIBER NETWORK CIRCUIT Figure 9-2 shows the recommended circuit for a 100 Mb/s fiber pair interface. Vdd 50: 50: 130: 130: 130: 130: 130: 80: 80: 80: 0.1 PF FXTDP FXTDM Fiber Transceiver 0.1 PF FXSD FXRDP FXRDM 80: 80: PLACE RESISTORS CLOSE TO THE FIBER TRANSCEIVER PLACE RESISTORS AND CAPACITORS CLOSE TO THE DEVICE All values are typical and are +/- 1% Figure 9-2. 100 Mb/s Fiber Pair Interface 9.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com Crystal A 25 MHz, parallel, 20 pF load crystal resonator should be used if a crystal source is desired. Figure 9-3 shows a typical connection for a crystal resonator circuit. The load capacitor values will vary with the crystal vendors; check with the vendor for the recommended loads. The oscillator circuit is designed to drive a parallel resonance AT cut crystal with a minimum drive level of 100 µW and a maximum of 500 µW.
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DP83620 www.ti.com SNLS339C – JANUARY 2011 – REVISED APRIL 2013 Table 9-1.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com 10 Register Block Table 10-1.
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DP83620 www.ti.com SNLS339C – JANUARY 2011 – REVISED APRIL 2013 Table 10-2.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com Table 10-2.
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DP83620 www.ti.com SNLS339C – JANUARY 2011 – REVISED APRIL 2013 Table 10-2.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com 10.
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DP83620 www.ti.com SNLS339C – JANUARY 2011 – REVISED APRIL 2013 Table 10-3. Basic Mode Control Register (BMCR), address 0x00 (continued) Bit Bit Name Default 9 RESTART AUTO-NEGOTIATION 0, RW/SC DUPLEX MODE Strap, RW Description Restart Auto-Negotiation: 1 = Restart Auto-Negotiation. Re-initiates the Auto-Negotiation process. If AutoNegotiation is disabled (bit 12 = 0), this bit is ignored.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com Table 10-4. Basic Mode Status Register (BMSR), address 0x01 (continued) Bit Bit Name Default 4 REMOTE FAULT 0, RO/LH Description Remote Fault: 1 = Remote Fault condition detected (cleared on read or by reset). Fault criteria: Far End Fault Indication or notification from Link Partner of Remote Fault. 0 = No remote fault condition detected.
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DP83620 www.ti.com SNLS339C – JANUARY 2011 – REVISED APRIL 2013 10.1.5 Auto-Negotiation Advertisement Register (ANAR) This register contains the advertised abilities of this device as they will be transmitted to its link partner during Auto-Negotiation. Any writes to this register prior to completion of Auto-Negotiation (as indicated in the Basic Mode Status Register (address 01h) Auto-Negotiation Complete bit, BMSR[5]) should be followed by a renegotiation.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com 10.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page) This register contains the advertised abilities of the Link Partner as received during Auto-Negotiation. The content changes after the successful auto-negotiation if Next-pages are supported. Table 10-8.
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DP83620 www.ti.com SNLS339C – JANUARY 2011 – REVISED APRIL 2013 10.1.7 Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page) Table 10-9. Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page), address 0x05 Bit Bit Name Default 15 NP 0, RO Description Next Page Indication: 1 = Link Partner desires Next Page Transfer. 0 = Link Partner does not desire Next Page Transfer. 14 ACK 0, RO Acknowledge: 1 = Link Partner acknowledges reception of the ability data word.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com 10.1.9 Auto-Negotiation Next Page Transmit Register (ANNPTR) This register contains the next page information sent by this device to its Link Partner during AutoNegotiation. Table 10-11. Auto-Negotiation Next Page Transmit Register (ANNPTR), address 0x07 Bit Bit Name Default 15 NP 0, RW Description Next Page Indication: 0 = No other Next Page Transfer desired. 1 = Another Next Page desired.
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DP83620 www.ti.com SNLS339C – JANUARY 2011 – REVISED APRIL 2013 Table 10-12. PHY Status Register (PHYSTS), address 0x10 (continued) Bit Bit Name Default 13 RECEIVE ERROR LATCH 0, RO/LH Description Receive Error Latch: This bit will be cleared upon a read of the RECR register. 1 = Receive error event has occurred since last read of RXERCNT (address 15h, Page 0). 0 = No receive error event has occurred.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com Table 10-12. PHY Status Register (PHYSTS), address 0x10 (continued) Bit Bit Name Default 2 DUPLEX STATUS 0, RO Description Duplex: This bit indicates duplex status and is determined from Auto-Negotiation or Forced Modes. 1 = Full duplex mode. 0 = Half duplex mode. Note: This bit is only valid if Auto-Negotiation is enabled and complete and there is a valid link or if Auto-Negotiation is disabled and there is a valid link.
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DP83620 www.ti.com SNLS339C – JANUARY 2011 – REVISED APRIL 2013 10.1.12 MII Interrupt Status and Event Control Register (MISR) This register contains event status and enables for the interrupt function. If an event has occurred since the last read of this register, the corresponding status bit will be set. If the corresponding enable bit in the register is set, an interrupt will be generated if the event occurs. The MICR register controls must also be set to allow interrupts.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com Table 10-14. MII Interrupt Status and Event Control Register (MISR), address 0x12 (continued) Bit Bit Name Default 4 SPD_INT_EN 0, RW Enable Interrupt on change of speed status. Description 3 DUP_INT_EN 0, RW Duplex Interrupt: Enable Interrupt on change of duplex status. 2 ANC_INT_EN 0, RW Enable Interrupt on auto-negotiation complete event.
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DP83620 www.ti.com SNLS339C – JANUARY 2011 – REVISED APRIL 2013 10.2.2 Receiver Error Counter Register (RECR) This counter provides information required to implement the “Symbol Error During Carrier” attribute within the PHY managed object class of Clause 30 of the IEEE 802.3u specification. Table 10-17. Receiver Error Counter Register (RECR), address 0x15 Bit Bit Name Default 15:8 RESERVED 0000 0000, RO Description 7:0 RXERCNT[7:0] 0000 0000, RO/COR RESERVED: Writes ignored, read as 0.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com Table 10-18. 100 Mb/s PCS Configuration and Status Register (PCSR), address 0x16 (continued) Bit Bit Name Default 5 FORCE_100_OK 0, RW Description Force 100 Mb/s Good Link: OR’ed with MAC_FORCE_LINK_100 signal. 1 = Forces 100 Mb/s Good Link. 0 = Normal 100 Mb/s operation. 4 RESERVED 0, RO 3 FEFI_EN Strap, RW RESERVED: Writes ignored, read as 0.
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DP83620 www.ti.com SNLS339C – JANUARY 2011 – REVISED APRIL 2013 Table 10-19. RMII and Bypass Register (RBR), address 0x17 (continued) Bit Bit Name Default 8 PMD_LOOP 0, RW Description PMD Loopback: 0 = Normal Operation. 1 = Remote (PMD) Loopback. Setting this bit will cause the device to Loopback data received from the Physical Layer. The loopback is done prior to the MII or RMII interface. Data received at the internal MII or RMII interface will be applied to the transmitter.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com 10.2.5 LED Direct Control Register (LEDCR) This register provides the ability to directly control any or all LED outputs. It does not provide read access to LEDs. In addition, it provides control for the Activity source and blinking LED frequency. Table 10-20.
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DP83620 www.ti.com SNLS339C – JANUARY 2011 – REVISED APRIL 2013 10.2.6 PHY Control Register (PHYCR) This register provides control for PHY functions such as MDIX, BIST, LED configuration, and PHY address. It also provides Pause Negotiation status. Table 10-21. PHY Control Register (PHYCR), address 0x19 Bit Bit Name Default 15 MDIX_EN 1, RW Description Auto-MDIX Enable: 1 = Enable Auto-neg Auto-MDIX capability. 0 = Disable Auto-neg Auto-MDIX capability.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com Table 10-21.
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DP83620 www.ti.com SNLS339C – JANUARY 2011 – REVISED APRIL 2013 Table 10-22. 10Base-T Status/Control Register (10BTSCR), address 0x1A (continued) Bit Bit Name Default 2 10BT_SCALE - MSB 1, RW 10BT Scale Configuration Most Significant Bit Used in conjunction with bit 10 of SD_CNFG register to set the silence ’OFF’ threshold for the receiver. Description 1 HEARTBEAT_DIS 0, RW Heartbeat Disable: This bit only has influence in half-duplex 10 Mb mode. 1 = Heartbeat function disabled.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com Table 10-23. CD Test and BIST Extensions Register (CDCTRL1), address 0x1B (continued) Bit Bit Name Default 1:0 CDPATTSEL[1:0] 00, RW Description CD Pattern Select[1:0]: If CDPATTEN_10 = 1: 00 = Data, EOP0 sequence. 01 = Data, EOP1 sequence. 10 = NLPs. 11 = Constant Manchester 1s (10 MHz sine wave) for harmonic distortion testing. 10.2.9 PHY Control Register 2 (PHYCR2) This register provides additional general control. Table 10-24.
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DP83620 www.ti.com SNLS339C – JANUARY 2011 – REVISED APRIL 2013 10.2.10 Energy Detect Control (EDCR) This register provides control and status for the Energy Detect function. Table 10-25. Energy Detect Control (EDCR), address 0x1D Bit Bit Name Default 15 ED_EN 0, RW Description Energy Detect Enable: Allow Energy Detect Mode. 14 ED_AUTO_UP 1, RW Energy Detect Automatic Power Up: Automatically begin power up sequence when Energy Detect Data Threshold value (EDCR[3:0]) is reached.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com 10.2.11 PHY Control Frames Configuration Register (PCFCR) This register provides configuration for the PHY Control Frame mechanism for register access. Table 10-26. PHY Control Frames Configuration Register (PCFCR), address 0x1F Bit Bit Name Default 15 PCF_STS_ERR 0, RO/COR Description PHY Control Frame Error Detected: Indicates an error was detected in a PCF Frame since the last read of this register. This bit will be cleared on read.
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DP83620 www.ti.com SNLS339C – JANUARY 2011 – REVISED APRIL 2013 10.3 TEST REGISTERS - PAGE 1 Page 1 Test Registers are accessible by setting bits [2:0] = 001 of PAGESEL (13h). 10.3.1 Signal Detect Configuration (SD_CNFG), Page 1 This register contains Signal Detect configuration control as well as some test controls to speed up Autoneg testing. Table 10-27. Signal Detect Configuration (SD_CNFG), address 0x1E Bit Bit Name Default 15 RESERVED 1, RW RESERVED: Write as 1, read as 1.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com 10.4 LINK DIAGNOSTICS REGISTERS - PAGE 2 Page 2 Link Diagnostics Registers are accessible by setting bits [2:0] = 010 of PAGESEL (13h). 10.4.1 100 Mb Length Detect Register (LEN100_DET), Page 2 This register contains linked cable length estimation in 100 Mb operation. The cable length is an estimation of the effective cable length based on the characteristics of the recovered signal.
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DP83620 www.ti.com SNLS339C – JANUARY 2011 – REVISED APRIL 2013 10.4.3 TDR Control Register (TDR_CTRL), Page 2 This register contains control for the Time Domain Reflectometry (TDR) cable diagnostics. The TDR cable diagnostics sends pulses down the cable and captures reflection data to be used to estimate cable length and detect certain cabling faults. Table 10-30. TDR Control Register (TDR_CTRL), address 0x16 Bit Bit Name Default 15 TDR_ENABLE 0, RW Description TDR Enable: Enable TDR mode.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com 10.4.4 TDR Window Register (TDR_WIN), Page 2 This register contains sample window control for the Time Domain Reflectometry (TDR) cable diagnostics. The two values contained in this register specify the beginning and end times for the window to monitor the response to the transmitted pulse. Time values are in 8 ns increments. This provides a method to search for multiple responses and also to screen out the initial outgoing pulse.
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DP83620 www.ti.com SNLS339C – JANUARY 2011 – REVISED APRIL 2013 10.4.7 Variance Control Register (VAR_CTRL), Page 2 The Variance Control and Data Registers provide control and status for the Cable Signal Quality Estimation function. The Cable Signal Quality Estimation allows a simple method of determining an approximate Signal-to-Noise Ratio for the 100 Mb receiver.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com 10.4.9 Link Quality Monitor Register (LQMR), Page 2 This register contains the controls for the Link Quality Monitor function. The Link Quality Monitor provides a mechanism for programming a set of thresholds for DSP parameters. If the thresholds are violated, an interrupt will be asserted if enabled in the MISR.
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DP83620 www.ti.com SNLS339C – JANUARY 2011 – REVISED APRIL 2013 Table 10-36. Link Quality Monitor Register (LQMR), address 0x1D (continued) Bit Bit Name Default 2 DAGC_LO_WARN 0, RO/COR Description DAGC Low Warning: This bit indicates the DAGC Low Threshold was exceeded. This register bit will be cleared on read. 1 C1_HI_WARN 0, RO/COR C1 High Warning: This bit indicates the DEQ C1 High Threshold was exceeded. This register bit will be cleared on read.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com Table 10-37. Link Quality Data Register (LQDR), address 0x1E (continued) Bit Bit Name Default 8 LQ_THR_SEL 0, RW Description Link Quality Threshold Select: This bit selects the Link Quality Threshold to be read or written. A 0 selects the Low threshold, while a 1 selects the high threshold.
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DP83620 www.ti.com SNLS339C – JANUARY 2011 – REVISED APRIL 2013 10.5 PHY STATUS FRAME CONFIGURATION REGISTER - PAGE 5 The Page 5 PHY Status Frame Configuration Register is accessible by setting bits [2:0] = 101 of PAGESEL (13h). 10.5.1 PHY Status Frame Configuration Register(PSF_CFG), Page 5 This register provides configuration for the PHY Status Frame function. Table 10-39.
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DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (April 2013) to Revision C • 100 Changed layout of National Data Sheet to TI format Page ..........................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing DP83620SQ/NOPB WQFN RHS 48 DP83620SQE/NOPB WQFN RHS DP83620SQX/NOPB WQFN RHS SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 48 2500 330.0 16.4 7.3 7.3 1.3 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DP83620SQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 DP83620SQE/NOPB WQFN RHS 48 250 213.0 191.0 55.0 DP83620SQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.
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MECHANICAL DATA RHS0048A SQA48A (Rev B) www.ti.
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