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DP83640

www.ti.com

SNOSAY8E –SEPTEMBER 2007–REVISED APRIL 2013

DP83640 Precision PHYTER™ - IEEE 1588 Precision Time Protocol Transceiver

Check for Samples: DP83640

1 Introduction

1.1 Features

123

• IEEE 1588 V1 and V2 Supported • Error-free Operation up to 150 Meters CAT5

Cable

• UDP/IPv4, UDP/IPv6, and Layer2 Ethernet

Packets Supported • ESD Protection - 8 kV Human Body Model

• IEEE 1588 Clock Synchronization • 2.5 V and 3.3 V I/Os and MAC Interface

• Timestamp Resolution of 8 ns • Auto-MDIX for 10/100 Mbps

• Allows Sub 10 ns Synchronization to Master • RMII Rev. 1.2 and MII MAC Interface

Reference

• 25 MHz MDC and MDIO Serial Management

• 12 IEEE 1588 GPIOs for Trigger or Capture Interface

• Deterministic, Low Transmit and Receive • IEEE 802.3u 100BASE-FX Fiber Interface

Latency

• IEEE 1149.1 JTAG

• Selectable Frequency Synchronized Clock

• Programmable LED Support for Link, 10 /100

Output

Mb/s Mode, Duplex, Activity, and Collision

• Dynamic Link Quality Monitoring Detect

• TDR Based Cable Diagnostic and Cable Length • Optional 100BASE-TX Fast Link-loss Detection

Detection

• Industrial Temperature Range

• 10/100 Mb/s Packet BIST (Built in Self Test)

• 48 pin LQFP Package (7mm) x (7mm)

1.2 Applications

• Factory Automation

– Ethernet/IP

– CIP Sync

• Test and Measurement

– LXI Standard

• Telecom

– Basestation

• Real Time Networking

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PHYTER is a trademark of Texas Instruments.

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to

specifications per the terms of the Texas Instruments standard warranty. Production

processing does not necessarily include testing of all parameters.

Summary of content (137 pages)

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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 DP83640 Precision PHYTER™ - IEEE 1588 Precision Time Protocol Transceiver Check for Samples: DP83640 1 Introduction 1.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 1.3 www.ti.com Description The DP83640 Precision PHYTER™ device delivers the highest level of precision clock synchronization for real time industrial connectivity based on the IEEE 1588 standard. The DP83640 has deterministic, low latency and allows choice of microcontroller with no hardware customization required. The integrated 1588 functionality allows system designers the flexibility and precision of a close to the wire timestamp.
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DP83640 www.ti.com 1 .............................................. 1 ............................................. 1 1.2 Applications .......................................... 1 1.3 Description ........................................... 2 Device Information ...................................... 5 2.1 System Diagram ..................................... 5 2.2 Block Diagram ....................................... 6 2.3 Key IEEE 1588 Features ............................ 7 Pin Descriptions ..............
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 9 10 4 www.ti.com ..................................... ................................. 9.2 Fiber Network Circuit ............................... 9.3 ESD Protection ..................................... 9.4 Clock In (X1) Recommendations ................... Register Block ......................................... 10.1 Register Definition .................................. Design Guidelines 71 9.1 71 TPI Network Circuit 72 72 72 75 83 .....
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 2 Device Information System Diagram MPU/CPU MII or RMII IEEE 1588 Captured Events DP83640 10/100 Mb/s Precision PHYTER RJ45 Media Access Control (MAC) IEEE 1588 clocks, events, triggers IEEE 1588 Triggered Events Magnetics 2.1 Fiber Transceiver Clock 10BASE-T 100BASE-TX or 100BASE-FX Status LEDs Figure 2-1.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 2.2 www.ti.
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DP83640 www.ti.com 2.3 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 Key IEEE 1588 Features IEEE 1588 provides a time synchronization protocol, often referred to as the Precision Time Protocol (PTP), which synchronizes time across an Ethernet network. DP83640 supports IEEE 1588 Real Time Ethernet applications by providing hardware support for three time critical elements.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 2.3.1 www.ti.com IEEE 1588 SYNCHRONIZED CLOCK The DP83640 provides several mechanisms for updating the IEEE 1588 clock based on the synchronization protocol required. These methods are listed below. • Directly Read/Writable • Adjustable by Add/Subtract • Frequency Scalable • Temporary Frequency Control The clock consists of the following fields: Seconds (32–bit field), Nanoseconds (30–bit field), and Fractional Nanoseconds (units of 2-32 ns).
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DP83640 www.ti.com 2.3.2 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 PACKET TIMESTAMPS 2.3.2.1 IEEE 1588 Transmit Packet Parser and Timestamp The IEEE 1588 transmit parser monitors transmit packet data to detect IEEE 1588 Version 1 and Version 2 Event messages. The transmit parser can detect PTP Event messages transported directly in Layer2 Ethernet packets as well as in UDP/IPv4 and UDP/IPv6 packets.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com The device supports up to 8 trigger signals which can be output on any of the GPIO signal pins. Multiple triggers may be assigned to a single GPIO, allowing generation of more complex waveforms (i.e. a sequence of varying width pulses). The trigger signals are OR’ed together to form a combined signal. The triggers are configured through the PTP Trigger Configuration Registers.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 3 Pin Descriptions The DP83640 pins are classified into the following interface categories (each interface is described in the sections that follow): • Serial Management Interface • MAC Data Interface • Clock Interface • LED Interface • GPIO Interface • JTAG Interface • Reset and Power Down • Strap Options • 10/100 Mb/s PMD Interface • Power and Ground pins Note: Strapping pin option. Please see Section 3.10 for strap definitions.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 GPIO8 IO_CORE_VSS X1 X2 IO_VDD MDC MDIO RESET_N LED_LINK LED_SPEED/FX_SD LED_ACT GPIO4 36 35 34 33 32 31 30 29 28 27 26 25 Pin Layout GPIO9 37 24 CLK_OUT RX_CLK 38 23 GPIO3 RX_DV 39 22 GPIO2 CRS/CRS_DV 40 21 GPIO1 RX_ER 41 20 VREF 19 ANA33VDD 18 ANAVSS COL 42 RXD_3 43 RXD_2 44 17 TD+ RXD_1 45 16 TD- RXD_0 46 15 CD_VSS IO_VSS 47 14 RD+ IO_VDD 48 13 RD- 1 2 3 4 5 6 7 8 9 10
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DP83640 www.ti.com 3.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 3.3 www.ti.com Serial Management Interface (SMI) Signal Name Pin Name Type Pin # Description MDC MDC I 31 MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO management data input/output serial interface which may be asynchronous to transmit and receive clocks. The maximum clock rate is 25 MHz with no minimum clock rate.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 Type Pin # Description CRS/CRS_DV Signal Name CRS/CRS_DV S, O, PU 40 MII CARRIER SENSE: Asserted high to indicate the receive medium is non-idle. RMII CARRIER SENSE/RECEIVE DATA VALID: This signal combines the RMII Carrier and Receive Data Valid indications. For a detailed description of this signal, see the RMII Specification.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 Signal Name LED_ACT 3.7 Pin Name LED_ACT www.ti.com Type Pin # Description S, O, PU 26 ACTIVITY LED: In Mode 1, this pin is the Activity LED which is ON when activity is present on either Transmit or Receive. COLLISION/DUPLEX LED: In Mode 2, this pin by default indicates Collision detection. In Mode 3, this LED output indicates Full-Duplex status.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 3.10 Strap Options The DP83640 uses many of the functional pins as strap options to place the device into specific modes of operation. The values of these pins are sampled at power up or hard reset. During software resets, the strap options are internally reloaded from the values sampled at power up or hard reset. The strap option pin assignments are defined below. The functional pin name is indicated in parentheses. A 2.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 Signal Name Pin Name www.ti.com Type Pin # Description FX_EN_Z RX_ER S, O, PU 41 FX ENABLE: This strapping option enables 100Base-FX (Fiber) mode. This mode is disabled by default. An external pull-down will enable 100Base-FX mode. LED_CFG CRS/CRS_DV S, O, PU 40 LED CONFIGURATION: This strapping option determines the mode of operation of the LED pins. Default is Mode 1. Mode 1 and Mode 2 can be controlled via the strap option.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 4 Electrical Specifications 4.1 Absolute Maximum Ratings (1) (2) Supply Voltage (VCC) -0.5 V to 4.2 V DC Input Voltage (VIN) -0.5V to VCC + 0.5V DC Output Voltage (VOUT) -0.5V to VCC + 0.5V Storage Temperature (TSTG ) -65°C to 150°C Maximum Case Temperature for TA = 85 °C 95 °C Maximum Die Temperature (Tj) 150 °C Lead Temperature (TL) (Soldering, 10 s) 260 °C ESD Rating (RZAP = 1.5k, CZAP = 120 pF) 8.0 kV (1) (2) 4.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 4.4 www.ti.com DC SPECIFICATIONS Symbol Pin Types Parameter VIH I I/O Input High Voltage VIL I I/O Input Low Voltage IIH I I/O Input High Current IIL I I/O VOL Conditions Min Typ Max 2.0 Units V VI/O = 3.3 V 0.8 VI/O = 2.5 V 0.7 V VIN = VI/O 10 µA Input Low Current VIN = GND 10 µA O I/O Output Low Voltage IOL = 4 mA 0.
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DP83640 www.ti.com 4.5 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 AC Specifications — Power Up Timing Notes Min T2.1.1 Parameter Post Power Up Stabilization time prior to MDC preamble for register accesses (1) MDIO is pulled high for 32-bit serial management initialization. 167 ms T2.1.2 Hardware Configuration Latch-in Time from power up (1) Hardware Configuration Pins are described in the Section 3. 167 ms T2.1.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 4.6 www.ti.com AC Specifications — Reset Timing Parameter Description Notes Min Typ Max Units T2.2.1 Post RESET Stabilization time prior to MDC preamble for register accesses MDIO is pulled high for 32-bit serial management initialization 3 µs T2.2.2 Hardware Configuration Latch-in Time from the Deassertion of RESET (either soft or hard) Hardware Configuration Pins are described in the Section 3 3 µs T2.2.
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DP83640 www.ti.com 4.7 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 AC Specifications — MII Serial Management Timing Parameter Description Notes Min T2.3.1 MDC to MDIO (Output) Delay Time 0 T2.3.2 MDIO (Input) to MDC Setup Time 10 T2.3.3 MDIO (Input) to MDC Hold Time 10 T2.3.4 MDC Frequency Typ Max Units 20 ns ns ns 2.5 25 MHz MDC T2.3.4 T2.3.1 MDIO (output) MDC T2.3.2 T2.3.3 Valid Data MDIO (input) Figure 4-3. MII Serial Management Timing 4.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 4.9 www.ti.com AC Specifications — 100 Mb/s MII Receive Timing Min Typ Max Units T2.5.1 Parameter RX_CLK High/Low Time (1) 100 Mb/s Normal mode 16 20 24 ns T2.5.2 RX_CLK to RXD[3:0], RX_DV, RX_ER Delay 100 Mb/s Normal mode 10 30 ns (1) Description Notes RX_CLK may be held low or high for a longer period of time during transition between reference and recovered clocks. Minimum high and low times will not be violated. T2.5.1 T2.5.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 4.11 AC Specifications — 100BASE-TX and 100BASE-FX MII Transmit Packet Deassertion Timing Parameter T2.7.1 (1) Description Notes TX_CLK to PMD Output Pair Deassertion (1) Min Typ 100BASE-TX and 100BASE-FX modes Max Units 5 bits Deassertion is determined by measuring the time from the first rising edge of TX_CLK occurring after the deassertion of TX_EN to the first bit of the "T" code group as output from the PMD Output Pair.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com 4.13 AC Specifications — 100BASE-TX and 100BASE-FX MII Receive Packet Latency Timing Parameter Description T2.9.1 Carrier Sense ON Delay T2.9.2 Receive Data Latency (3) (4) (1) (2) (3) (4) Notes (2) Min Typ 100BASE-TX mode 20 100BASE-FX mode 10 100BASE-TX mode 24 100BASE-FX mode 14 Max Units (1) bits bits 1 bit time = 10 ns in 100 Mb/s mode.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 4.15 AC Specifications — 10 Mb/s MII Transmit Timing Parameter Description (1) Min Typ Max Units T2.11.1 TX_CLK High/Low Time 10 Mb/s MII mode 190 200 210 ns T2.11.2 TXD[3:0], TX_EN Data Setup to TX_CLK falling edge 10 Mb/s MII mode 25 ns T2.11.3 TXD[3:0], TX_EN Data Hold from TX_CLK rising edge 10 Mb/s MII mode 0 ns (1) Notes An attached Mac should drive the transmit signals using the positive edge of TX_CLK.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com 4.17 AC Specifications — 10BASE-T MII Transmit Timing (Start of Packet) Parameter T2.13.1 Description Notes Transmit Output Delay from the Min 10 Mb/s MII mode Typ Max 3.5 Units (1) bits Falling Edge of TX_CLK (1) 1 bit time = 100 ns in 10 Mb/s. TX_CLK TX_EN TXD[3:0] PMD Output Pair T2.13.1 Figure 4-13. 10BASE-T MII Transmit Timing (Start of Packet) 4.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 4.19 AC Specifications — 10BASE-T MII Receive Timing (Start of Packet) Parameter Description Notes T2.15.1 Carrier Sense Turn On Delay (PMD Input Pair to CRS) T2.15.2 RX_DV Latency (2) T2.15.3 Receive Data Latency (1) (2) Min Typ Max Units (1) 630 1000 ns 10 bits 8 bits Measurement shown from SFD 1 bit time = 100 ns in 10 Mb/s mode.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com 4.21 AC Specifications — 10 Mb/s Heartbeat Timing Parameter Description Notes Min Typ Max Units T2.17.1 CD Heartbeat Delay All 10 Mb/s modes 1200 ns T2.17.2 CD Heartbeat Duration All 10 Mb/s modes 1000 ns TX_EN TX_CLK T2.17.1 T2.17.2 COL Figure 4-17. 10 Mb/s Heartbeat Timing 4.22 AC Specifications — 10 Mb/s Jabber Timing Parameter Description Notes Min Typ Max Units T2.18.1 Jabber Activation Time 85 ms T2.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 4.24 AC Specifications — Auto-Negotiation Fast Link Pulse (FLP) Timing Parameter Description Notes Typ (1) Min Max Units T2.20.1 Clock, Data Pulse Width 100 ns T2.20.2 Clock Pulse to Clock Pulse 125 µs 62 µs Period T2.20.3 Clock Pulse to Data Pulse Data = 1 Period T2.20.4 Burst Width 2 ms T2.20.5 FLP Burst to FLP Burst Period 16 ms (1) These specifications represent transmit timings T.2.20.2 T2.20.3 T2.20.1 T2.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com 4.26 AC Specifications — 100 Mb/s Internal Loopback Timing Parameter Description Notes TX_EN to RX_DV Loopback (1) T2.22.1 (1) (2) Min 100 Mb/s internal loopback mode (2) Typ Max Units 240 ns Due to the nature of the descrambler function, all 100BASE-TX Loopback modes will cause an initial “dead-time” of up to 550 µs during which time no data will be present at the receive MII outputs.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 4.27 AC Specifications — 10 Mb/s Internal Loopback Timing Parameter T2.23.1 (1) Description TX_EN to RX_DV Loopback Notes Min 10 Mb/s internal loopback mode (1) Typ Max Units 2 µs Measurement is made from the first falling edge of TX_CLK after assertion of TX_EN. TX_CLK TX_EN TXD[3:0] CRS/CRS_DV T2.23.1 RX_CLK RX_DV RXD[3:0] Figure 4-23.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com 4.28 AC Specifications — RMII Transmit Timing (Slave Mode) Parameter Description Notes Min T2.24.1 X1 Clock Period T2.24.2 TXD[1:0], TX_EN, Data Setup to X1 rising edge 4 T2.24.3 TXD[1:0], TX_EN, Data Hold from X1 rising edge 2 T2.24.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 4.29 AC Specifications — RMII Transmit Timing (Master Mode) Parameter Description Notes Min Max Units RX_CLK, TX_CLK, CLK_OUT Period T2.25.2 TXD[1:0], TX_EN Data Setup to RX_CLK, TX_CLK, CLK_OUT rising edge 4 ns T2.25.3 TXD[1:0], TX_EN Data Hold from RX_CLK, TX_CLK, CLK_OUT rising edge 2 ns T2.25.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com 4.30 AC Specifications — RMII Receive Timing (Slave Mode) Parameter Description (1) Notes T2.26.1 X1 Clock Period T2.26.2 RXD[1:0], CRS_DV, and RX_ER output delay from X1 rising edge (2) T2.26.3 CRS ON delay (3) T2.26.4 CRS OFF delay T2.26.5 (1) (2) (3) (4) (5) (6) (7) Min Typ 50 MHz Reference Clock 2 RXD[1:0] and RX_ER latency (5) (6) (7) 18.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 4.31 AC Specifications — RMII Receive Timing (Master Mode) Parameter Description (1) Notes T2.27.1 RX_CLK, TX_CLK, CLK_OUT Clock Period T2.27.2 RXD[1:0], CRS_DV, RX_DV and RX_ER output delay from RX_CLK, TX_CLK, CLK_OUT rising edge (2) T2.27.3 CRS ON delay (3) T2.27.4 T2.27.5 (1) (2) (3) (4) (5) CRS OFF delay (4) RXD[1:0] and RX_ER latency Min Typ 50 MHz Reference Clock (5) Max Units 20 ns 2 14 100BASE-TX mode 18.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com 4.33 AC Specifications — CLK_OUT Timing (RMII Slave Mode) Parameter Description T2.29.1 CLK_OUT High/Low Time T2.29.2 CLK_OUT propagation delay Notes Min Typ Max 10 Relative to X1 Units ns 8 ns Max Units X1 T2.29.2 T2.29.1 T2.29.1 CLK_OUT Figure 4-29. CLK_OUT Timing (RMII Slave Mode) 4.34 AC Specifications — Single Clock MII (SCMII) Transmit Timing Parameter Description Notes Min T2.30.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 4.35 AC Specifications — Single Clock MII (SCMII) Receive Timing Parameter Description Notes Min T2.31.1 X1 Clock Period 25 MHz Reference Clock (1) T2.31.2 RXD[3:0], RX_DV and RX_ER output delay (2) From X1 rising edge T2.31.3 CRS ON delay T2.31.4 CRS OFF delay T2.31.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com 5 Configuration This section includes information on the various configuration options available with the DP83640. The configuration options described below include: • Media Configuration • Auto-Negotiation • PHY Address and LEDs • Half Duplex vs. Full Duplex • Isolate mode • Loopback mode • BIST 5.1 Media Configuration The DP83640 supports both Twister Pair (100BASE-TX and 10BASE-T) and Fiber (100BASE-FX) media.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 Table 5-1. Auto-Negotiation Modes AN_EN AN1 AN0 0 0 0 10BASE-T, Half-Duplex Forced Mode 0 0 1 10BASE-T, Full-Duplex 0 1 0 100BASE-TX, Half-Duplex 100BASE-TX, Full-Duplex 0 1 1 AN_EN AN1 AN0 1 0 0 10BASE-T, Half/Full-Duplex 1 0 1 100BASE-TX, Half/Full-Duplex 1 1 0 100BASE-TX Full-Duplex 1 1 1 10BASE-T, Half/Full-Duplex Advertised Mode 100BASE-TX, Half/Full-Duplex 5.2.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 • • • • • 5.2.3 Whether Whether Whether Whether Whether or not or not or not or not or not www.ti.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 Neither Auto-Negotiation nor Auto-MDIX is required to be enabled in forcing crossover of the MDI pairs. Forced crossover can be achieved through the FORCE_MDIX bit, bit 14 of PHYCR (19h) register. NOTE: Auto-MDIX will not work in a forced mode of operation. 5.4 PHY Address The five PHY address strapping pins are shared with the RXD[3:0] pins and COL pin as shown below. Table 5-2.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com When in the MII Isolate Mode, the DP83640 does not respond to packet data present at TXD[3:0] and TX_EN inputs and presents a high impedance on the TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0], COL, and CRS/CRS_DV outputs. When in Isolate Mode, the DP83640 will continue to respond to all serial management transactions over the MII.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 The LED_SPEED/FX_SD pin indicates 10 or 100 Mb/s data rate of the port. The standard CMOS driver goes high when operating in 100 Mb/s operation. The functionality of this LED is independent of mode selected. The LED_ACT pin in Mode 1 indicates the presence of either transmit or receive activity. The LED will be ON for Activity and OFF for No Activity. In Mode 2, this pin indicates the Collision status of the port.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 5.6 www.ti.com Half Duplex vs. full Duplex The DP83640 supports both half and full duplex operation at both 10 Mb/s and 100 Mb/s speeds. Half-duplex relies on the CSMA/CD protocol to handle collisions and network access. In Half-Duplex mode, Carrier Sense (CRS) responds to both transmit and receive activity in order to maintain compliance with the IEEE 802.3 specification.
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DP83640 www.ti.com 5.8.2 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 Interrupt Mechanisms The interrupt function is controlled via register access. All interrupt sources are disabled by default. Setting bit 1 (INTEN) of MICR (11h) will enable interrupts to be output, dependent on the interrupt mask set in the lower byte of the MISR (12h). The PWRDOWN/INTN pin is asynchronously asserted low when an interrupt condition occurs.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com 5.10.1.2 Cable Swap Indication As part of Auto-Negotiation, the DP83640 has the ability (using Auto-MDIX) to automatically detect a cable with swapped MDI pairs and select the appropriate pairs for transmitting and receiving data. Normal operation is termed MDI, while crossed operation is MDIX. The MDIX status can be read from bit 14 of the PHYSTS (10h). 5.10.1.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 5.10.2.1 Link Quality Monitor Control and Status Control of the Link Quality Monitor is done through the Link Quality Monitor Register (LQMR), address 1Dh and the Link Quality Data Register (LQDR), address 1Bh of the Link Diagnostics Registers - Page 2. The LQMR register includes a global enable to enable the Link Quality Monitor function.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com 2. Write 8000 to LQMR to enable the Link Quality Monitor (if not already enabled). 5.10.3 TDR Cable Diagnostics The DP83640 implements a Time Domain Reflectometry (TDR) method of cable length measurement and evaluation which can be used to evaluate a connected twisted pair cable. The TDR implementation involves sending a pulse out on either the Transmit or Receive conductor pair and observing the results on either pair.
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DP83640 www.ti.com • SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 Transmit Channel Select: The transmitter can send pulses down either the transmit pair or the receive pair by enabling bit 13 of TDR_CTRL (16h). Default value is to select the transmit pair. The following receive mode controls are available: • Min/Max Mode Control: Bit 7 of TDR_CTRL (16h) controls the TDR Monitor operation. In default mode, the monitor will detect maximum (positive) values.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com 6 MAC Interface The DP83640 supports several modes of operation using the MII interface pins. The options are defined in the following sections and include: • MII Mode • RMII Mode • Single Clock MII Mode (SCMII) In addition, the DP83640 supports the standard 802.3u MII Serial Management Interface. The modes of operation can be selected by strap options or register control.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 When heartbeat is enabled (only applicable to 10 Mb/s operation), approximately 1µs after the transmission of each packet, a Signal Quality Error (SQE) signal of approximately 10 bit times is generated (internally) to indicate successful transmission. SQE is reported as a pulse on the COL signal of the MII. Collision is not indicated during Full Duplex operation. 6.1.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com The elasticity buffer will force Frame Check Sequence errors for packets which overrun or underrun the FIFO. Underrun and overrun conditions can be reported in the RMII and Bypass Register (RBR). Table 61 indicates how to program the elasticity buffer FIFO (in 4-bit increments) based on expected maximum packet size and clock accuracy. It assumes both clocks (RMII Reference clock and far-end Transmitter clock) have the same accuracy.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 Table 6-2. Supported SCMII Packet Sizes at +/-50 ppm Frequency Accuracy Start Threshold RBR[1:0] 6.4 6.4.1 Latency Tolerance Recommended Packet Size at +/- 50 ppm 100 Mb 10 Mb 100 Mb 10 Mb 01 (default) 4 bits 8 bits 4,000 bytes 9,600 bytes 10 4 bits 8 bits 4,000 bytes 9,600 bytes 11 8 bits 8 bits 9,600 bytes 9,600 bytes 00 8 bits 8 bits 9,600 bytes 9,600 bytes IEEE 802.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com The Start code is indicated by a <01> pattern. This assures the MDIO line transitions from the default idle line state. Turnaround is defined as an idle bit time inserted between the Register Address field and the Data field. To avoid contention during a read transaction, no device shall actively drive the MDIO signal during the first bit of Turnaround.
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DP83640 www.ti.com 6.5 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 PHY Control Frames The DP83640 supports a packet-based control mechanism for use in situations where the Serial Management Interface is not available or does not provide enough throughput. Application software may build a packet, called a PHY Control Frame (PCF), to be passed to the PHY through the MAC Transmit Data interface.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com The packet format may be configured to look like a Layer 2 Ethernet frame or a UDP/IPv4 frame. For a more detailed discussion on the use of PHY Status Frames, refer to the Software Development Guide for the DP83640.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 7 Architecture This section describes the operations within each transceiver module, 100BASE-TX and 10BASE-T. Each operation consists of several functional blocks and is described in the following: • 100BASE-TX Transmitter • 100BASE-TX Receiver • 100BASE-FX Operation • 10BASE-T Transceiver Module 7.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com Table 7-1.
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DP83640 www.ti.com 7.1.1 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 Code-Group Encoding and Injection The code-group encoder converts 4-bit (4B) nibble data generated by the MAC into 5-bit (5B) code-groups for transmission. This conversion is required to allow control data to be combined with packet data codegroups. Refer to Table 7-1 for 4B to 5B code-group mapping details.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com The Receive section consists of the following functional blocks: • Analog Front End • Input and BLW Compensation • Signal Detect • Digital Adaptive Equalization • MLT-3 to Binary Decoder • Clock Recovery Module • NRZI to NRZ Decoder • Serial to Parallel • Descrambler (bypass option) • Code Group Alignment • 4B/5B Decoder • Link Integrity Monitor • Bad SSD Detection 7.2.
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DP83640 www.ti.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 7.2.2.2 www.ti.com Digital Adaptive Equalization and Gain Control The DP83640 utilizes an extremely robust equalization scheme referred as ‘Digital Adaptive Equalization.’ The Digital Equalizer removes ISI (inter symbol interference) from the receive data stream by continuously adapting to provide a filter with the inverse frequency response of the channel. Equalization is combined with an adaptive gain control stage.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 In order to maintain synchronization, the descrambler must continuously monitor the validity of the unscrambled data that it generates. To ensure this, a line state monitor and a hold timer are used to constantly monitor the synchronization status. Upon synchronization of the descrambler, the hold timer starts a 722 µs countdown.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 7.3.2 www.ti.com 100BASE-FX Receive In 100BASE-FX mode, the device Receive pins connect to an industry standard Fiber Transceiver with PECL signaling through a capacitively coupled circuit. In FX mode, the device bypasses the MLT3 Decoder and the Descrambler. This allows for the reception of serialized 5B4B encoded NRZI data at 125 MHz. The only added functionality for 100BASE-FX from 100BASE-TX is the support of Far-End Fault detection. 7.3.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 The signal at the start of a packet is checked by the smart squelch and any pulses not exceeding the squelch level (either positive or negative, depending upon polarity) will be rejected. Once this first squelch level is overcome correctly, the opposite squelch level must then be exceeded within 150 ns. Finally the signal must again exceed the original squelch level within 150 ns to ensure that the input waveform will not be rejected.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 7.4.5 www.ti.com Normal Link Pulse Detection/Generation The link pulse generator produces pulses as defined in the IEEE 802.3 10BASE-T standard. Each link pulse is nominally 100 ns in duration and transmitted every 16 ms in the absence of transmit data. Link pulses are used to check the integrity of the connection with the remote end.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 The decoder detects the end of a frame when no additional mid-bit transitions are detected. Within one and a half bit times after the last bit, carrier sense is de-asserted. Receive clock stays active for five more bit times after CRS goes low, to verify the receive timings of the controller.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com 8 Reset Operation The DP83640 includes an internal power-on reset (POR) function and does not need to be explicitly reset for normal operation after power up. If required during normal operation, the device can be reset by a hardware or software reset. 8.1 Hardware Reset A hardware reset is accomplished by applying a low pulse (TTL level), with a duration of at least 1 µs, to the RESET_N pin.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 9 Design Guidelines 9.1 TPI Network Circuit Figure 9-1 shows the recommended circuit for a 10/100 Mb/s twisted pair interface. Below is a partial list of recommended transformers. It is important that the user realize that variations with PCB and component characteristics requires that the application be tested to ensure that the circuit meets the requirements of the intended application.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 9.2 www.ti.com Fiber Network Circuit Figure 9-2 shows the recommended circuit for a 100 Mb/s fiber pair interface. Vdd 50: 50: 130: 130: 130: 130: 130: 80: 80: 80: 0.1 PF FXTDP FXTDM Fiber Transceiver 0.1 PF FXSD FXRDP FXRDM 80: 80: PLACE RESISTORS CLOSE TO THE FIBER TRANSCEIVER PLACE RESISTORS AND CAPACITORS CLOSE TO THE DEVICE All values are typical and are +/- 1% Figure 9-2. 100 Mb/s Fiber Pair Interface 9.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 A 25 MHz, parallel, 20 pF load crystal resonator should be used if a crystal source is desired. Figure 9-3 shows a typical connection for a crystal resonator circuit. The load capacitor values will vary with the crystal vendors; check with the vendor for the recommended loads. The oscillator circuit is designed to drive a parallel resonance AT cut crystal with a minimum drive level of 100 µW and a maximum of 500 µW.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com Table 9-1.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 10 Register Block Table 10-1.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com Table 10-1.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 Table 10-2.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com Table 10-2. Register Table (continued) Register Name Addr Tag Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MII Interrupt Status and Misc.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 Table 10-2.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com Table 10-2.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 Table 10-2.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com Table 10-2.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 10.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com Table 10-3. Basic Mode Control Register (BMCR), address 0x00 (continued) Bit Bit Name Default 9 RESTART AUTO-NEGOTIATION 0, RW/SC DUPLEX MODE Strap, RW Description Restart Auto-Negotiation: 1 = Restart Auto-Negotiation. Re-initiates the Auto-Negotiation process. If AutoNegotiation is disabled (bit 12 = 0), this bit is ignored.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 Table 10-4. Basic Mode Status Register (BMSR), address 0x01 (continued) Bit Bit Name Default 4 REMOTE FAULT 0, RO/LH Description Remote Fault: 1 = Remote Fault condition detected (cleared on read or by reset). Fault criteria: Far End Fault Indication or notification from Link Partner of Remote Fault. 0 = No remote fault condition detected.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com 10.1.5 Auto-Negotiation Advertisement Register (ANAR) This register contains the advertised abilities of this device as they will be transmitted to its link partner during Auto-Negotiation. Any writes to this register prior to completion of Auto-Negotiation (as indicated in the Basic Mode Status Register (address 01h) Auto-Negotiation Complete bit, BMSR[5]) should be followed by a renegotiation.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 10.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page) This register contains the advertised abilities of the Link Partner as received during Auto-Negotiation. The content changes after the successful auto-negotiation if Next-pages are supported. Table 10-8.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com 10.1.7 Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page) Table 10-9. Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page), address 0x05 Bit Bit Name Default 15 NP 0, RO Description Next Page Indication: 1 = Link Partner desires Next Page Transfer. 0 = Link Partner does not desire Next Page Transfer. 14 ACK 0, RO Acknowledge: 1 = Link Partner acknowledges reception of the ability data word.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 10.1.9 Auto-Negotiation Next Page Transmit Register (ANNPTR) This register contains the next page information sent by this device to its Link Partner during AutoNegotiation. Table 10-11. Auto-Negotiation Next Page Transmit Register (ANNPTR), address 0x07 Bit Bit Name Default 15 NP 0, RW Description Next Page Indication: 0 = No other Next Page Transfer desired. 1 = Another Next Page desired.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com Table 10-12. PHY Status Register (PHYSTS), address 0x10 (continued) Bit Bit Name Default 13 RECEIVE ERROR LATCH 0, RO/LH Description Receive Error Latch: This bit will be cleared upon a read of the RECR register. 1 = Receive error event has occurred since last read of RXERCNT (address 15h, Page 0). 0 = No receive error event has occurred.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 Table 10-12. PHY Status Register (PHYSTS), address 0x10 (continued) Bit Bit Name Default 2 DUPLEX STATUS 0, RO Description Duplex: This bit indicates duplex status and is determined from Auto-Negotiation or Forced Modes. 1 = Full duplex mode. 0 = Half duplex mode. Note: This bit is only valid if Auto-Negotiation is enabled and complete and there is a valid link or if Auto-Negotiation is disabled and there is a valid link.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com 10.1.12 MII Interrupt Status and Event Control Register (MISR) This register contains event status and enables for the interrupt function. If an event has occurred since the last read of this register, the corresponding status bit will be set. If the corresponding enable bit in the register is set, an interrupt will be generated if the event occurs. The MICR register controls must also be set to allow interrupts.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 Table 10-14. MII Interrupt Status and Event Control Register (MISR), address 0x12 (continued) Bit Bit Name Default Description 8 RHF_INT or PCF_INT 0, RO/COR Receive Error Counter half-full interrupt: Receive error counter half-full interrupt. This function is selected if the PHYCR2[8:7] are both 0. 1 = Receive error counter half-full interrupt is pending and is cleared by the current read.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com 10.2 Extended Registers - Page 0 10.2.1 False Carrier Sense Counter Register (FCSCR) This counter provides information required to implement the “False Carriers” attribute within the MAU managed object class of Clause 30 of the IEEE 802.3u specification. Table 10-16.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 Table 10-18. 100 Mb/s PCS Configuration and Status Register (PCSR), address 0x16 (continued) Bit Bit Name Default 7 DESC_TIME 0, RW Description Descrambler Timeout: Increase the descrambler timeout. When set, this allows the device to receive larger packets (>9k bytes) without loss of synchronization. 1 = 2 ms. 0 = 722 µs (per ANSI X3.263: 1995 (TP-PMD) 7.2.3.3e).
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com Table 10-19. RMII and Bypass Register (RBR), address 0x17 (continued) Bit Bit Name Default 13 DIS_TX_OPT 0, RW Description Disable RMII TX Latency Optimization: Normally the RMII Transmitter will minimize the transmit latency by realigning the transmit clock with the reference clock phase at the start of a packet transmission.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 10.2.5 LED Direct Control Register (LEDCR) This register provides the ability to directly control any or all LED outputs. It does not provide read access to LEDs. In addition, it provides control for the Activity source and blinking LED frequency. Table 10-20.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com Table 10-21. PHY Control Register (PHYCR), address 0x19 (continued) Bit Bit Name Default 13 PAUSE_RX 0, RO Description Pause Receive Negotiated: Indicates that pause receive should be enabled in the MAC. Based on ANAR[11:10] and ANLPAR[11:10] settings. This function shall be enabled according to IEEE 802.3 Annex 28B Table 28B-3, “Pause Resolution”, only if the Auto-Negotiated Highest Common Denominator is a full duplex technology.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 Table 10-21.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com Table 10-22. 10Base-T Status/Control Register (10BTSCR), address 0x1A (continued) Bit Bit Name Default 3 AUTOPOL_DIS 0, RW Auto Polarity Detection & Correction Disable: 1 = Polarity Correction disabled 0 = Polarity Correction enabled Description 2 10BT_SCALE - MSB 1, RW 10BT Scale Configuration Most Significant Bit Used in conjunction with bit 10 of SD_CNFG register to set the silence ’OFF’ threshold for the receiver.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 Table 10-23. CD Test and BIST Extensions Register (CDCTRL1), address 0x1B (continued) Bit Bit Name Default 1:0 CDPATTSEL[1:0] 00, RW Description CD Pattern Select[1:0]: If CDPATTEN_10 = 1: 00 = Data, EOP0 sequence. 01 = Data, EOP1 sequence. 10 = NLPs. 11 = Constant Manchester 1s (10 MHz sine wave) for harmonic distortion testing. 10.2.9 PHY Control Register 2 (PHYCR2) This register provides additional general control. Table 10-24.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com 10.2.10 Energy Detect Control (EDCR) This register provides control and status for the Energy Detect function. Table 10-25. Energy Detect Control (EDCR), address 0x1D Bit Bit Name Default 15 ED_EN 0, RW Description Energy Detect Enable: Allow Energy Detect Mode. 14 ED_AUTO_UP 1, RW Energy Detect Automatic Power Up: Automatically begin power up sequence when Energy Detect Data Threshold value (EDCR[3:0]) is reached.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 10.2.11 PHY Control Frames Configuration Register (PCFCR) This register provides configuration for the PHY Control Frame mechanism for register access. Table 10-26. PHY Control Frames Configuration Register (PCFCR), address 0x1F Bit Bit Name Default 15 PCF_STS_ERR 0, RO/COR Description PHY Control Frame Error Detected: Indicates an error was detected in a PCF Frame since the last read of this register.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com 10.3 Test Registers - Page 1 Page 1 Test Registers are accessible by setting bits [2:0] = 001 of PAGESEL (13h). 10.3.1 Signal Detect Configuration (SD_CNFG), Page 1 This register contains Signal Detect configuration control as well as some test controls to speed up Autoneg testing. Table 10-27. Signal Detect Configuration (SD_CNFG), address 0x1E Bit Bit Name Default 15 RESERVED 1, RW RESERVED: Write as 1, read as 1.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 10.4 Link Diagnostics Registers - Page 2 Page 2 Link Diagnostics Registers are accessible by setting bits [2:0] = 010 of PAGESEL (13h). 10.4.1 100 Mb Length Detect Register (LEN100_DET), Page 2 This register contains linked cable length estimation in 100 Mb operation. The cable length is an estimation of the effective cable length based on the characteristics of the recovered signal.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com 10.4.3 TDR Control Register (TDR_CTRL), Page 2 This register contains control for the Time Domain Reflectometry (TDR) cable diagnostics. The TDR cable diagnostics sends pulses down the cable and captures reflection data to be used to estimate cable length and detect certain cabling faults. Table 10-30. TDR Control Register (TDR_CTRL), address 0x16 Bit Bit Name Default 15 TDR_ENABLE 0, RW Description TDR Enable: Enable TDR mode.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 10.4.4 TDR Window Register (TDR_WIN), Page 2 This register contains sample window control for the Time Domain Reflectometry (TDR) cable diagnostics. The two values contained in this register specify the beginning and end times for the window to monitor the response to the transmitted pulse. Time values are in 8 ns increments. This provides a method to search for multiple responses and also to screen out the initial outgoing pulse.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com Table 10-34. Variance Control Register (VAR_CTRL), address 0x1A Bit Bit Name Default 15 VAR_RDY 0, RO Description Variance Data Ready Status: Indicates new data is available in the Variance data register. This bit will be automatically cleared after two consecutive reads of VAR_DATA. 14:4 RESERVED 000 0000 0000, RO 3 VAR_FREEZE 0, RW RESERVED: Writes ignored, read as 0. Freeze Variance Registers: Freeze VAR_DATA register.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 Table 10-36. Link Quality Monitor Register (LQMR), address 0x1D (continued) Bit Bit Name Default 14 RESTART_ON_FC 0, RW Restart on Frequency Control Warning: Allow automatic reset of DSP and restart of 100 Mb Adaption on detecting a Frequency Threshold violation. If the SD_Option bit, PCSR[8], is set to 0, the threshold violation will also result in a drop in Link status.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com Table 10-37. Link Quality Data Register (LQDR), address 0x1E Bit Bit Name Default 15:14 RESERVED 00, RO RESERVED: Writes ignored, read as 0. Description 13 SAMPLE_PARAM 0, RW Sample DSP Parameter: Setting this bit to a 1 enables reading of current parameter values and initiates sampling of the parameter value. The parameter to be read is selected by the LQ_PARAM_SEL bits.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 10.4.11 Link Quality Monitor Register 2 (LQMR2), Page 2 This register contains additional controls for the Link Quality Monitor function. The Link Quality Monitor provides a mechanism for programming a set of thresholds for DSP parameters. If the thresholds are violated, an interrupt will be asserted if enabled in the MISR.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com 10.5 PTP 1588 Base Registers - Page 4 Page 4 PTP 1588 Base Registers are accessible by setting bits [2:0] = 100 of PAGESEL (13h). 10.5.1 PTP Control Register (PTP_CTL), Page 4 This register provides basic control of the PTP 1588 operation. Table 10-39.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 10.5.2 PTP Time Data Register (PTP_TDR), Page 4 This register provides a mechanism for reading and writing the 1588 Time and Trigger Control values. The function of this register is determined by controls in the PTP_CTL register. Table 10-40.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com 10.5.4 PTP Trigger Status Register (PTP_TSTS), Page 4 This register provides status of the PTP 1588 Triggers. The bits in this register indicate the current status of each of the Trigger modules. The error bits will be set if the associated notification enable (TRIGN_NOTIFY) is set in the PTP Trigger Configuration Registers. Table 10-42.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 10.5.5 PTP Rate Low Register (PTP_RATEL), Page 4 This register contains the low 16-bits of the PTP Rate control. The PTP Rate Control indicates a positive or negative adjustment to the reference clock period in units of 2-32 ns. On each reference clock cycle, the PTP Clock will be adjusted by adding REF_CLK_PERIOD +/- PTP_RATE. The PTP Rate should be written as PTP_RATEH, followed by PTP_RATEL.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com 10.5.8 PTP Write Checksum (PTP_WRCKSUM), Page 4 This register keeps a running one’s complement checksum of 16-bit write data values for Page 4 write accesses. Clear the checksum on a read. Write data to this register or the read checksum register ARE accumulated in the write checksum to allow cross checking. Read data from this register is accumulated in the read checksum to allow cross checking.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 10.5.11 PTP Event Status Register (PTP_ESTS), Page 4 This register provides Status for the Event Timestamp unit. Reading this register provides status for the next Event Timestamp contained in the Event Data Register. If this register is 0, no Event Timestamp is available in the Event Data Register. Reading this register will automatically move to the next Event in the queue. Table 10-49.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 • • www.ti.com Timestamp_sec[15:0] Timestamp_sec[31:16] For Extended Event Status, the following definition is used for the PTP Event Data Register: Table 10-50.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 For timestamp fields, the following definition is used for the PTP Event Data Register: Table 10-51. PTP Event Data Register (PTP_EDATA), address 0x1F Bit Bit Name Default 15:0 PTP_EVNT_TS XXXX XXXX XXXX XXXX, RO Description PTP Event Timestamp: Reading this register will return 16 bits of the Event Timestamp.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com 10.6 PTP 1588 Configuration Registers - Page 5 Page 5 PTP 1588 Configuration Registers are accessible by setting bits [2:0] = 101 of PAGESEL (13h). 10.6.1 PTP Trigger Configuration Register (PTP_TRIG), Page 5 This register provides basic configuration for IEEE 1588 Triggers. To write configuration to a Trigger, set the TRIG_WR bit along with the TRIG_SEL and other control information.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 Table 10-53. PTP Event Configuration Register (PTP_EVNT), address 0x15 (continued) Bit Bit Name Default 12 EVNT_SINGLE 0, RW Single Event Capture: Setting this bit to a 1 will enable single event capture operation. The EVNT_RISE and EVNT_FALL enables will be cleared upon a valid event timestamp capture.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com Table 10-54. PTP Transmit Configuration Register 0 (PTP_TXCFG0), address 0x16 (continued) Bit Bit Name Default Description 4:1 TX_PTP_VER 0 000, RW PTP Version: Enable Timestamp capture for a specific version of the IEEE 1588 specification. This field may be programmed to any value between 1 and 15 and allows support for future versions of the IEEE 1588 specification. A value of 0 will disable version checking (not recommended).
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 Table 10-56. PHY Status Frame Configuration Register 0 (PSF_CFG0), address 0x18 (continued) Bit Bit Name Default 2 PSF_RXTS_EN 0, RW Receive Timestamp PHY Status Frame Enable: Enable PHY Status Frame delivery of Receive Timestamps. Description 1 PSF_TRIG_EN 0, RW Trigger PHY Status Frame Enable: Enable PHY Status Frame delivery of Trigger Status.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com 10.6.7 PTP Receive Configuration Register 1 (PTP_RXCFG1), Page 5 This register provides data and mask fields to filter the first byte in a PTP Message. This function will be disabled if all the mask bits are set to 0. Table 10-58. PTP Receive Configuration Register 1 (PTP_RXCFG1), address 0x1A Bit Bit Name Default Description 15:8 BYTE0_MASK 0000 0000, RW Byte0 Data: Bit mask to be used for matching Byte0 of the Receive PTP Message.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 Table 10-60. PTP Receive Configuration Register 3 (PTP_RXCFG3), address 0x1C (continued) Bit Bit Name Default Description 8 TS_INSERT 0, RW Enable Timestamp Insertion: Enables Timestamp insertion into a packet containing a PTP Event Message. If this bit is set, the Timestamp will not be available through the PTP Receive Timestamp Register. 7:0 PTP_DOMAIN 0000 0000, RW PTP Domain: Value of the PTP Message domainNumber field.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com Table 10-62. PTP Temporary Rate Duration Low Register (PTP_TRDL), address 0x1E Bit Bit Name Default 15:0 PTP_TR_DURL 0000 0000 0000 0000, RW Description PTP Temporary Rate Duration Low 16 bits: This register sets the duration for the Temporary Rate in number of clock cycles. The actual Time duration is dependent on the value of the Temporary Rate. 10.6.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 10.7 PTP 1588 Configuration Registers - Page 6 Page 6 PTP 1588 Configuration Registers are accessible by setting bits [2:0] = 110 of PAGESEL (13h). 10.7.1 PTP Clock Output Control Register (PTP_COC), Page 6 This register provides configuration for the PTP clock-synchronized output divide-by-N clock. Table 10-64.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com Table 10-66. PHY Status Frame Configuration Register 2 (PSF_CFG2), address 0x16 (continued) Bit Bit Name Default 7:0 IP_SA_BYTE0 0000 0000, RW Description First byte of IP source address: This field contains the most significant byte of the IP source address. 10.7.4 PHY Status Frame Configuration Register 3 (PSF_CFG3), Page 6 This register provides configuration for the PHY Status Frame function.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 10.7.8 PTP Clock Source Register (PTP_CLKSRC), Page 6 This register provides configuration for the reference clock source driving the IEEE 1588 logic. The source clock period is also used by the 1588 clock nanoseconds adder to add the proper value every reference clock cycle. Table 10-71.
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DP83640 SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 www.ti.com 10.7.12 PTP Receive Hash Register (PTP_RXHASH), Page 6 This register provides configuration for the source identity hash filter of the PTP receive packet parser. If enabled, the receive parse logic will deliver a receive timestamp only if the hash function on the ten octet sourcePortIdentity field correctly matches the programmed value. The source identity hash filter does not affect timestamp insertion. Table 10-75.
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DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (April 2013) to Revision E • Changed layout of National Data Sheet to TI format Page .........................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 24-Nov-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device DP83640TVVX/NOPB Package Package Pins Type Drawing LQFP PT 48 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 16.4 Pack Materials-Page 1 9.3 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 9.3 2.2 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DP83640TVVX/NOPB LQFP PT 48 1000 367.0 367.0 38.
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MECHANICAL DATA MTQF003A – OCTOBER 1994 – REVISED DECEMBER 1996 PT (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 1,45 1,35 Seating Plane 1,60 MAX 0°– 7° 0,75 0,45 0,10 4040052 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.