7.0 DC and AC Specifications (Continued)
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DP83815
PCI Bus Master Burst Write
PCI Bus Arbitration
PCICLK
FRAMEN
AD[31:0]
C/BEN[3:0]
IRDYN
TRDYN
DEVSELN
PAR
PERRN
Addr
Data
Cmd
BE
T3
T3
T3
T3
T3
T4
T4
T3
T3
T3
T4
T1
T2
T1
T2
T3
T4
T1
T2
T4
T3
Data
Data
PCICLK
REQN
GNTN
T5
T6
T2
T5
