Datasheet

3.0 Functional Description (Continued)
Subject to change without notice. 14 Rev O www.national.com
DP83815
Figure 3-2 MAC/BIU Functional Block Diagram
3.1 MAC/BIU
The MAC/BIU is a derivative design from the DP83810
(Euphrates). The original MAC/BIU design has been
optimized to improve logic efficiency and enhanced to add
features consistent with current market needs and
specification compliance. The MAC/BIU design blocks are
discussed in this section.
3.1.1 PCI Bus Interface
This block implements PCI v2.2 bus protocols, and
configuration space. Supports bus master reads and writes
to CPU memory, and CPU access to on-chip register
space. Additional functions provided include: configuration
control, serial EEPROM access with auto configuration
load, interrupt control, power management control with
support for PME or CLKRUN function.
3.1.1.1 Byte Ordering
The DP83815 can be configured to order the bytes of data
on the AD[31:0] bus to conform to little endian or big
endian ordering through the use of the Configuration
Register, bit 0 (CFG:BEM). By default, the device is in little
endian ordering. Byte ordering only affects data FIFOs.
Register information remains bit aligned (i.e. AD[31] maps
to bit 31 in any register space, AD[0] maps to bit 0, etc.).
Tx Buffer Manager
MIB
Tx MAC
Rx MAC
PCI Bus
Data FIFO
Physical Layer Interface
93C46
Serial
EEPROM
MAC/BIU
32
15
32
32
32
32
32
16
32
32
4
4
32
Rx Filter
Pkt Recog
Logic
SRAM
Rx Buffer Manager
Data FIFO
Boot ROM/
Flash
PCI Bus
Interface
Obsolete