Datasheet

3.0 Functional Description (Continued)
Subject to change without notice. 30 Rev O www.national.com
DP83815
3.12.3 MII Serial Management Access
Management access to the PHY(s) is done via
Management Data Clock (MDC) and Management Data
Input/Output (MDIO). MDC has a maximum clock rate of 25
MHz and no minimum rate. The MDIO line is bi-directional
and may be shared by up to 32 devices. The internal PHY
counts as one of these 32 devices.
The internal PHY has the advantage of having direct
register access but can also be controlled exactly like a
PHY, with a default address of 1Fh, connected to the MII.
Access and control of the MDC and MDIO pins is done via
the MII/EEPROM Access Register (MEAR). The clock
(MDC) is created by alternating writes of 0 then 1 to the
MDC bit (bit 6). Control of data direction is done by the
MDDIR bit (bit 5). Data is either recorded or written by the
MDIO bit (bit 4). Setting the MDDIR bit to a 1 allows the
DP83815 to drive the MDIO pin. Setting the MDDIR bit to a
0 allows the MDIO bit to reflect the value of the MDIO pin.
See Section 4.2.3
This bit-bang access of the MDC and MDIO pins thus
requires 64 accesses to the MEAR register to complete a
single PHY register transaction. Since a PHY device is
typically self configuring and adaptive this serial
management access is usually only required at
initialization time and therefore is not time critical.
3.12.4 Serial Management Access Protocol
The serial control interface clock (MDC) has a maximum
clock rate of 25 MHz and no minimum rate. The MDIO line
is bi-directional and may be shared by up to 32 devices.
The MDIO frame format is shown in Table 3-2.
If external PHY devices may be attached and removed
from the MII there should be a 15 KΩ pull-down resistor on
the MDIO signal. If the PHY will always be connected then
there should be a 1.5 kΩ pull-up resistor which, during
IDLE and turnaround, will pull MDIO high. In order to
initialize the MDIO interface, the DP83815 sends a
sequence of 32 contiguous logic ones on MDIO provides
the PHY(s) with a sequence that can be used to establish
synchronization. This preamble may be generated either
by driving MDIO high for 32 consecutive MDC clock cycles,
or by simply allowing the MDIO pull-up resistor to pull the
MDIO pin high during which time 32 MDC clock cycles are
provided. In addition 32 MDC clock cycles should be used
to re-sync the device if an invalid start, opcode, or
turnaround bit is detected.
The Start code is indicated by a <01> pattern. This assures
the MDIO line transitions from the default idle line state.
Turnaround is defined as an idle bit time inserted between
the Register Address field and the Data field. To avoid
contention during a read transaction, no device shall
actively drive the MDIO signal during the first bit of
Turnaround. The addressed PHY drives the MDIO with a
zero for the second bit of turnaround and follows this with
the required data. Figure 3-15 shows the timing
relationship between MDC and the MDIO as
driven/received by the DP83815 and a PHY for a typical
register read access.
For write transactions, the DP83815 writes data to the
addressed PHY thus eliminating the requirement for MDIO
Turnaround. The Turnaround time is filled by the DP83815
by inserting <10>. Figure 3-16 shows the timing
relationship for a typical MII register write access.
3.12.5 Nibble-wide MII Data Interface
Clause 22 of the IEEE 802.3u specification defines the
Media Independent Interface. This interface include
separate dedicated receive and transmit busses. These
two data buses, along with various control and indication
signals, allow for the simultaneous exchange of data
between the DP83815 and PHY(s).
Table 3-2 Typical MDIO Frame Format
MII Management
Serial Protocol
<idle><start><op code><device addr><reg addr><turnaround><data><idle>
Read Operation <idle><01><10><AAAAA><RRRRR><Z0><xxxx xxxx xxxx xxxx><idle>
Write Operation <idle><01><01><AAAAA><RRRRR><10><xxxx xxxx xxxx xxxx><idle>
Figure 3-15 Typical MDC/MDIO Read Operation
MDC
MDIO
00011 110000000
(STA)
Idle Start
Opcode
(Read)
PHY Address
(PHYAD = 0Ch)
Register Address
(00h = BMCR)
TA
Register Data
Z
MDIO
(PHY)
Z
Z
Z
0 0 011000100000000
Z
Idle
Z
Z
Obsolete