Datasheet
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4.0 Register Set (Continued)
DP83815
4.1.2 Configuration Command and Status Register
The CFGCS register has two parts. The upper 16-bits (31-16) are devoted to device status. A status bit is reset whenever
the register is written, and the corresponding bit location is a 1. The lower 16-bits (15-0) are devoted to command and are
used to configure and control the device.
Tag: CFGCS Size: 32 bits Hard Reset: 02900000h
Offset: 04h Access: Read Write Soft Reset: Unchanged
Bit Bit Name Description
31 DPERR Detected Parity Error
Refer to the description in the PCI V2.2 specification.
30 SSERR Signaled SERR
Refer to the description in the PCI V2.2 specification.
29 RMABT Received Master Abort
Refer to the description in the PCI V2.2 specification.
28 RTABT Received Target Abort
Refer to the description in the PCI V2.2 specification.
27 STABT Sent Target Abort
Refer to the description in the PCI V2.2 specification.
26-25 DSTIM DEVSELN Timing
This field will always be set to 01 indicating that DP83815 supports “medium” DEVSELN timing.
24 DPD Data Parity Detected
Refer to the description in the PCI V2.2 specification.
23 FBB Fast Back-to-Back Capable
DP83815 will set this bit to 1.
22-21 unused
(reads return 0)
20 NCPEN New Capabilities Enable
When set, this bit indicates that the Capabilities Pointer contains a valid value and new capabilities such
as power management are supported. When clear, new capabilities (CAPPTR, PMCAP, PMCS) are
disabled. The value in this register will either be loaded from the EEPROM or, if the EEPROM is
disabled, from a strap option at reset.
19-16 Unused
(reads return 0)
15-10 Unused
(reads return 0)
9 FBBEN Fast Back-to-Back Enable
Set to 1 by the PCI BIOS to enable the DP83815 to do Fast Back-to-Back transfers (FBB transfers as a
master is not implemented in the current revision).
8 SERREN SERRN Enable
When SERREN and PERRSP are set, DP83815 will generate SERRN during target cycles when an
address parity error is detected from the system. Also, when SERREN and PERRSP are set and
CFG:PESEL is reset, master cycles detecting data parity errors will generate SERRN.
7 Unused
(reads return 0)
Obsolete