Datasheet

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4.0 Register Set (Continued)
DP83815
4.2.3 EEPROM Access Register
The EEPROM Access Register provides an interface for software access to the NMC9306 style EEPROM The default
values given assume that the EEDO line has a pullup resistor to VDD.
4.2.4 EEPROM Map
In the above table:
N denotes the value is dependent on the ethernet MAC ID Number.
X denotes the value is dependent on the checksum value.
Tag: MEAR Size: 32 bits Hard Reset: 00000002h
Offset: 0008h Access: Read Write Soft Reset: 00000002h
Bit Bit Name Description
31-7 unused
6 MDC MII Management Clock
Controls the value of the MDC pin. When set, the MDC pin is 1; when clear the MDC pin is 0. R/W
5 MDDIR MII Management Direction
Controls the direction of the MDIO pin. When set, DP83815 drives the MDIO pin. When clear MDIO bit
reflects the current state of the MDIO pin. R/W
4 MDIO MII Management Data
Software access to the MDIO pin (see MDDIR above). R/W
3 EESEL EEPROM Chip Select
Controls the value of the EESEL pin. When set, the EESEL pin is 1; when clear the EESEL pin is 0. R/W
2 EECLK EEPROM Serial Clock
Controls the value of the EECLK pin. When set, the EECLK pin is 1; when clear the EECLK pin is 0. R/W
1 EEDO EEPROM Data Out
Returns the current state of the EEDO pin. When set, the EEDO pin is 1; when clear the EEDO pin is 0.
RO
0 EEDI EEPROM Data In
Controls the value of the EEDI pin. R/W
EEPROM
Address
Configuration/Operation Register Bits
Default Value
(16 bits)
0000h CFGSID[0:15] D008h
0001h CFGSID[16:31] 0400h
0002h CFGINT[24:31],CFGINT[16:23] 2CD0h
0003h CFGCS[20],PMCAP[31],PMCAP[21],PMCSR[8],
CFG[13:16],CFG[18:23],CR[2], SOPAS[0]
CF82h
0004h SOPAS[1:16] 0000h
0005h SOPAS[17:32] 0000h
0006h SOPAS[33:47],PMATCH[0] 000Nh
0007h PMATCH[1:16] NNNNh
0008h PMATCH[17:32] NNNNh
0009h PMATCH[33:47],WCSR[0] NNNNh
000Ah WCSR[1:4],WCSR[9:10],RFCR[20],RFCR[22],
RFCR[27:31],000b (3 bits)
A098h
000Bh checksum value XX55
Obsolete