Datasheet
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4.0 Register Set (Continued)
DP83815
PMATCH[47:0] can be accessed via the combination of the RFCR (offset 0048h) and RFDR (offset 004Ch) registers.
PMATCH holds the Ethernet address info. See Section 3.3.3.
The lower 8 bits of the checksum value should be 55h. For the upper 8 bits, add the top 8 data bits to the lower 8 data bits
for each address. Sum the resultant 8 bit values for all addresses and then add 55h. Take the 2’s complement of the final
sum. This 2’s complement number should be the upper 8 bits of the checksum value in the last address.
As an example, consider an EEPROM with two addresses. EEPROM address 0000h contains the data 1234h. EEPROM
address 0001h contains the data 5678h.
12h + 34h = 46h
56h + 78h = CEh
46h + CEh + 55h = 69h
The 2’s complement of 69h is 97h so the checksum value entered into EEPROM address 0002h would be 9755h.
4.2.5 PCI Test Control Register
Tag: PTSCR Size: 32 bits Hard Reset: 00000000h
Offset: 000Ch Access: Read Write Soft Reset: 00000000h
Bit Bit Name Description
31-13 unused
12 Reserved
Must be written as a 0.
11 Reserved
10 RBIST_RST SRAM BIST Reset
Setting this bit to 1 allows the SRAM BIST engine to be reset. R/W
9-8 Reserved
Must be written as 0.
7 RBIST_EN SRAM BIST Enable
Setting this bit to 1 starts the SRAM BIST engine. R/W
6 RBIST_DONE SRAM BIST Done
This bit is set to one when the BIST has completed its current test. It is cleared when either the BIST
is active or disabled. RO
5 RBIST_RXFAIL RX FIFO BIST Fail
This bit is set to 1 if the SRAM BIST detects a failure in the RX FIFO SRAM. RO
4 RBIST_TXFAIL TX FIFO Fail
This bit is set to 1 if the SRAM BIST detects a failure in the TX FIFO SRAM. RO
3 RBIST_RXFFAIL RX Filter RAM BIST Fail
This bit is set to 1 if the SRAM BIST detects a failure in the RX Filter SRAM. RO
2 EELOAD_EN Enable EEPROM Load
This bit is set to a 1 to manually initiate a load of configuration information from EEPROM. A 1 is
returned while the configuration load from EEPROM is active (approx. 1500 us). R/W
1 EEBIST_EN Enable EEPROM BIST
This bit is set to a 1 to initiate EEPROM BIST, which verifies the EEPROM data and checksum
without reloading configuration values to the device. A 1 is returned while the EEPROM BIST is
active. R/W
0 EEBIST_FAIL EE BIST Fail indication
This bit is set to a 1 upon completion of the EEPROM BIST (EEBIST_EN returns 0) if the BIST logic
encountered an invalid checksum. RO
Obsolete