Datasheet

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4.0 Register Set (Continued)
DP83815
4.2.6 Interrupt Status Register
This register indicates the source of an interrupt when the INTA pin goes active. Enabling the corresponding bits in the
Interrupt Mask Register (IMR) allows bits in this register to produce an interrupt. When an interrupt is active, one or more
bits in this register are set to a “1”. The Interrupt Status Register reflects all current pending interrupts, regardless of the
state of the corresponding mask bit in the IMR. Reading the ISR clears all interrupts. Writing to the ISR has no effect.
Tag: ISR Size: 32 bits Hard Reset: 03008000h
Offset: 0010h Access: Read Only Soft Reset: 03008000h
Bit Bit Name Description
31-26 Reserved
25 TXRCMP Transmit Reset Complete
Indicates that a requested transmit reset operation is complete.
24 RXRCMP Receive Reset Complete
Indicates that a requested receive reset operation is complete.
23 DPERR Detected Parity Error
This bit is set whenever CFGCS:DPERR is set, but cleared (like all other ISR bits) when the ISR register
is read.
22 SSERR Signaled System Error
The DP83815 signaled a system error on the PCI bus.
21 RMABT Received Master Abort
The DP83815 received a master abort generated as a result of target not responding.
20 RTABT Received Target Abort
The DP83815 received a target abort on the PCI bus.
19-17 unused
16 RXSOVR Rx Status FIFO Overrun
Set when an overrun condition occurs on the Rx Status FIFO.
15 HIBERR High Bits Error Set
A logical OR of bits 25-16.
14 PHY Phy interrupt
Set to 1 when internal phy generates an interrupt.
13 PME Power Management Event
Set when WOL conditioned detected.
12 SWI Software Interrupt
Set whenever the SWI bit in the CR register is set.
11 MIB MIB Service
Set when one of the enabled management statistics has reached its interrupt threshold. (See
Section 4.2.23)
10 TXURN Tx Underrun
Set when a transmit data FIFO underrun condition occurs.
9 TXIDLE Tx Idle
This event is signaled when the transmit state machine enters the idle state from a non-idle state. This
will happen whenever the state machine encounters an "end-of-list" condition (NULL link field or a
descriptor with OWN clear).
8 TXERR Tx Packet Error
This event is signaled after the last transmit descriptor in a failed transmission attempt has been updated
with valid status.
Obsolete