Datasheet

76 www.national.com
4.0 Register Set (Continued)
DP83815
4.3.15 PHY Control Register
8 SD_OPTION Signal Detect Option:
1 = Enhanced signal detect algorithm
0 = Reduced signal detect algorithm
7:6 Reserved Reserved: Read as 0
5 FORCE_100_OK Force 100 Mb/s Good Link:
OR’ed with MAC_FORCE_LINK_100 signal.
1 = Forces 100 Mb/s Good Link
0 = Normal 100 Mb/s operation
4:3 Reserved Reserved: Read as 0
2 NRZI_BYPASS NRZI Bypass Enable:
1 = NRZI Bypass Enabled
0 = NRZI Bypass Disabled
1:0 Reserved Reserved: Read as 0
Tag: PHYCR Size: 16 bits Hard Reset: 003Fh
Offset: 00E4h Access: Read Write
Bit Bit Name Description
15:12 Reserved Reserved
11 PSR_15 BIST Sequence select: Selects length of LFSR used in BIST
1 = PSR15 selected
0 = PSR9 selected
10 BIST_STATUS BIST Test Status: Default: 0, LL/RO
1 = BIST pass
0 = BIST fail. Latched, cleared by write to BIST start bit.
9 BIST_START BIST Start: BIST runs continuously until stopped. Minimum time to run should be 1 ms.
1 = BIST start
0 = BIST stop
8 BP_STRETCH Bypass LED Stretching:
This will bypass the LED stretching and the LEDs will reflect the internal value.
1 = Bypass LED stretching
0 = Normal operation
7 PAUSE_STS Pause Compare Status: Default: 0, RO
0 = Local Device and the Link Partner are not Pause capable
1 = Local Device and the Link Partner are both Pause capable
6:5 Reserved Reserved
4:0 PHYADDR[4:0] PHY Address: Default: <11111b>, RW
PHY address for the port.
Bit Bit Name Description
Obsolete