DP83846A DP83846A DsPHYTER - Single 10/100 Ethernet Transceiver Literature Number: SNLS063E
DP83846A DsPHYTER — Single 10/100 Ethernet Transceiver General Description Features The DP83846A is a full feature single Physical Layer device with integrated PMD sublayers to support both 10BASE-T and 100BASE-TX Ethernet protocols over Category 3 (10 Mb/s) or Category 5 Unsheilded twisted pair cables.
DP83846A RX_CLK RXD[3:0] RX_DV RX_ER CRS COL MDC MDIO TX_EN SERIAL MANAGEMENT TX_ER TX_CLK HARDWARE CONFIGURATION PINS (AN_EN, AN0, AN1) (PAUSE_EN) (LED_CFG, PHYAD) TXD[3:0] MII MII INTERFACE/CONTROL RX_CLK TX_DATA TRANSMIT CHANNELS & STATE MACHINES PARALLEL TO SERIAL SCRAMBLER NRZ TO NRZI ENCODER BINARY TO MLT-3 ENCODER 10 Mb/s REGISTERS MII PHY ADDRESS NRZ TO MANCHESTER ENCODER RECEIVE CHANNELS & STATE MACHINES AUTO NEGOTIATION BASIC MODE CONTROL 100 Mb/s 4B/5B DECODER CODE GROUP
DP83846A 3.0 4.0 5.0 6.0 O 7.0 ol e 2.0 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 MII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 10 Mb/s and 100 Mb/s PMD Interface . . . . . . . . . . 6 1.3 Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.4 Special Connections . . . . . . . . . . . . . . . . . . . . . . . 6 1.5 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.
DP83846A COL TXD_3 TXD_2 IO_VDD IO_GND TXD_1 TXD_0 IO_GND TX_EN TX_CLK TX_ER CORE_VDD CORE_GND RESERVED RX_ER/PAUSE_EN RX_CLK RX_DV IO_VDD IO_GND RXD_0 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 Connection Diagram CRS/LED_CFG 61 40 62 39 63 38 IO_GND 64 IO_VDD 65 X2 66 X1 67 37 36 35 34 69 RESERVED 70 RESERVED 71 CORE_VDD 72 CORE_GND 73 RESERVED 74 RESERVED 75 SUB_GND 76 31 MDC MDIO IO_VDD IO_GND LED_DPLX/PHYAD0 LED_C
The DP83846A pins are classified into the following interface categories (each interface is described in the sections that follow): Note: All DP83846A signal pins are I/O cells regardless of the particular use. Below definitions define the functionality of the I/O cells for each pin.
RXD[3] Type LQFP Pin # O, PU/PD RXD[2] RXD[1] RXD[0] RX_ER/PAUSE_EN RX_DV Description 38, 39, 40, 41 RECEIVE DATA: Nibble wide receive data (synchronous to corresponding RX_CLK, 25 MHz for 100BASE-TX mode, 2.5 MHz for 10BASE-T nibble mode). Data is driven on the falling edge of RX_CLK. RXD[2] has an internal pulldown resistor. The remaining RXD pins have pullups.
Type LQFP Pin # LED_DPLX/PHYAD0 Signal Name S, O 33 FULL DUPLEX LED STATUS: Indicates Full-Duplex status. LED_COL/PHYAD1 S, O 32 COLLISION LED STATUS: Indicates Collision activity in Half Duplex mode. LED_GDLNK/PHYAD2 S, O 31 GOOD LINK LED STATUS: Indicates Good Link Status for 10BASET and 100BASE-TX. LED_TX/PHYAD3 S, O 30 TRANSMIT LED STATUS: Indicates transmit activity. LED is on for activity, off for no activity. LED_RX/PHYAD4 S, O 29 RECEIVE LED STATUS: Indicates receive activity.
AN_EN Type S, O, PU LQFP Pin # Description 27 Auto-Negotiation Enable: When high enables Auto-Negotiation with the capability set by ANO and AN1 pins. When low, puts the part into Forced Mode with the capability set by AN0 and AN1 pins. AN_1 26 AN_0 25 AN0 / AN1: These input pins control the forced or advertised operating mode of the DP83846A according to the following table. The value on these pins is set by connecting the input pins to GND (0) or VCC (1) through 5 kΩ resistors.
DP83846A 1.7 Reset Signal Name Type LQFP Pin # LLP Pin # Description I 62 46 RESET: Active Low input that initializes or re-initializes the DP83846A. Asserting this pin low for at least 160 µs will force a reset process to occur which will result in all internal registers re-initializing to their default states as specified for each bit in the Register Block section and all strapping options are re-initialized. RESET 1.
DP83846A 1.
This section includes information on the various configuration options available with the DP83846A. The configuration options described below include: — — — — — — — Table 1. Auto-Negotiation Modes AN_EN Device Configuration Auto-Negotiation PHY Address and LEDs Half Duplex vs. Full Duplex Isolate mode Loopback mode BIST 2.
data and link pulse activity until the break_link_timer expires (~1500 ms). Consequently, the Link Partner will go into link fail and normal Auto-Negotiation resumes. The DP83846A will resume Auto-Negotiation after the break_link_timer has expired by issuing FLP (Fast Link Pulse) bursts.
LED_FDPLX LED_COL LED_GDLNK LED_TX LED_RX 1kΩ te 10kΩ 1kΩ 10kΩ 1kΩ 10kΩ 1kΩ 10kΩ 1kΩ 10kΩ PHYAD4= 0 PHYAD3 = 0 PHYAD2 = 0 PHYAD1 = 1 PHYAD0 = 1 ol e VCC Figure 2. PHYAD Strapping and LED Loading Example 2.3 LED INTERFACES 10 Mb/s Link is established as a result of the reception of at least seven consecutive normal Link Pulses or the reception of a valid 10BASE-T packet. This will cause the assertion of GD_LINK.
O bs ol e te The DP83846A includes a Loopback Test mode for facilitating system diagnostics. The Loopback mode is selected through bit 14 (Loopback) of the Basic Mode Control Register (BMCR). Writing 1 to this bit enables MII transmit data to be routed to the MII receive outputs. Loopback status may be checked in bit 3 of the PHY Status Register All modes of operation (100BASE-TX and 10BASE-T) can (PHYSTS). While in Loopback mode the data will not be run either half-duplex or full-duplex.
3.1 802.3u MII mat is shown below in Table 4: Typical MDIO Frame Format. The DP83846A incorporates the Media Independent Interface (MII) as specified in Clause 22 of the IEEE 802.3u standard. This interface may be used to connect PHY devices to a MAC in 10/100 Mb/s systems. This section describes both the serial MII management interface as well as the nibble wide MII data interface. The MDIO pin requires a pull-up resistor (1.5 kΩ) which, during IDLE and turnaround, will pull MDIO high.
MDIO Z Z (STA) Z Idle 0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Start Opcode (Write) PHY Address (PHYAD = 0Ch) Register Address (00h = BMCR) Register Data TA Z Idle Figure 4. Typical MDC/MDIO Write Operation bs ol e te pression by returning a one in this bit, then the station 3.1.6 Collision Detect management entity need not generate preamble for each For Half Duplex, a 10BASE-T or 100BASE-TX collision is management transaction.
TX_CLK DP83846A implements the 100BASE-TX transmit state machine diagram as specified in the IEEE 802.3u Standard, Clause 24. TXD[3:0] / tx_er DIV BY 5 FROM PGM 4B5B Code-group encoder & injector mux te BP_4B5B 5B parallel to serial ol e scrambler mux BP_SCR nrz to nrzi encoder 100BASE-TX Loopback O bs binary to mlt-3 / Common Driver TD± Figure 5. 100BASE-TX Transmit Block Diagram 3.2.
3.2.4 Binary to MLT-3 Convertor / Common Driver The Binary to MLT-3 conversion is accomplished by converting the serial binary data stream output from the NRZI encoder into two binary data streams with alternately phased logic one events. These two binary streams are then fed to the twisted pair output driver which converts the voltage to current and alternately drives either side of the transmit transformer primary winding, resulting in a minimal current (20 mA max) MLT-3 signal. Refer to Figure 6. 3.2.
DP83846A PCS 5B Code-group MII 4B Nibble Code 0 11110 0000 1 01001 0001 2 10100 0010 3 10101 0011 4 01010 0100 5 01011 0101 6 01110 0110 7 01111 0111 8 10010 1000 9 10011 1001 A 10110 1010 B 10111 C 11010 D 11011 E 11100 F 11101 te Table 5.
O bs ol e te — ADC — Input and BLW Compensation — Signal Detect — Digital Adaptive Equalization The 100BASE-TX transmit TP-PMD function within the — MLT-3 to Binary Decoder DP83846A is capable of sourcing only MLT-3 encoded — Clock Recovery Module data. Binary output from the TD± outputs is not possible in — NRZI to NRZ Decoder 100 Mb/s mode. — Serial to Parallel — DESCRAMBLER (bypass option) 3.
DP83846A RX_CLK RXD[3:0] / RX_ER ÷5 mux BP_4B5B 4b/5b Decoder te Serial to parallel Code group alignment BP_SCR ol e mux DEscrambler CLOCK nrzi to nrz decoder bs Clock Recovery Module LINK STATUS O MLT-3 to Binary decoder Digital adaptive Equalization AGC LINK Monitor Signal Detect InPUT BLW Compensation ADC rd± Figure 8. Receive Block Diagram 21 www.national.
The CRM is implemented using an advanced all digital Phase Locked Loop (PLL) architecture that replaces sensitive analog circuitry. Using digital PLL circuitry allows the DP83846A to be manufactured and specified to tighter tolerances. The signal detect function of the DP83846A is incorporated to meet the specifications mandated by the ANSI FDDI TPPMD Standard as well as the IEEE 802.3 100BASE-TX Standard for both voltage thresholds and timing parameters.
3.4.2 Collision Detection and SQE The code-group decoder functions as a look up table that translates incoming 5B code-groups into 4B nibbles. The code-group decoder first detects the J/K code-group pair preceded by IDLE code-groups and replaces the J/K with MAC preamble. Specifically, the J/K 10-bit code-group pair is replaced by the nibble pair (0101 0101). All subsequent 5B code-groups are converted to the corresponding 4B nibbles for the duration of the entire packet.
valid on the rising edge of Transmit Clock (TX_CLK). Transmission ends when TX_EN deasserts. The last transition is always positive; it occurs at the center of the bit cell The inverse polarity condition is latched in the 10BTSCR if the last bit is a one, or at the end of the bit cell if the last register. The DP83846A's 10BASE-T transceiver module bit is a zero. corrects for this error internally and will continue to decode received data correctly. This eliminates the need to correct 3.4.
For applications where high reliability is required, it is recommended that additional ESD protection diodes be added as shown below. There are numerous dual series connected diode pairs that are available specifically for ESD protection. The level of protection will vary dependent upon the diode ratings. The primary parameter that affects the level of ESD protection is peak forward surge current.
As a starting point for evaluating an oscillator circuit, if the requirements for the crystal are not known, CL1 and CL2 should be set at 22 pF, and R1 should be set at 0Ω. The DsPHYTER supports an external CMOS level oscillator source or a crystal resonator device. If an external clock source is used, X1 should be tied to the clock source and X2 should be left floating. In either case, the clock source must be a 25 MHz 0.
DP83846A 5.0 Register Block Table 6.
Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00h Addr BMCR Tag Reset Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Loopback Speed Select Auto-Neg Enable Power down Isolate Restart Auto-Neg Duplex Collision Test Reserved Reserved Reserved Reserved Reserved Reserved Reserved Basic Mode Status Register 01h BMSR 100BaseT4 100BaseTX FDX 100BaseTX HDX 10BaseT FDXx 10BaseT HDX Reserved Reserved Reserved Reserved MF Preamble Suppress Auto-Neg Complete Remote Fault Au
DP83846A 5.
DP83846A Table 7. Basic Mode Control Register (BMCR), Address 0x00 Bit Bit Name 15 Reset Default Description 0, RW/SC Reset: 1 = Initiate software Reset / Reset in Process. 0 = Normal operation. This bit, which is self-clearing, returns a value of one until the reset process is complete. The configuration is re-strapped. 14 Loopback 0, RW Loopback: 1 = Loopback enabled. 0 = Normal operation. The loopback function enables MII transmit data to be routed to the MII receive data path.
DP83846A Table 8. Basic Mode Status Register (BMSR), address 0x01 Bit Bit Name Default 15 100BASE-T4 0, RO/P Description 100BASE-T4 Capable: 0 = Device not able to perform 100BASE-T4 mode. 14 100BASE-TX 1, RO/P Full Duplex 13 1 = Device able to perform 100BASE-TX in full duplex mode. 100BASE-TX 1, RO/P Half Duplex 12 100BASE-TX Half Duplex Capable: 1 = Device able to perform 100BASE-TX in half duplex mode.
Table 9. PHY Identifier Register #1 (PHYIDR1), address 0x02 Bit Bit Name 15:0 OUI_MSB Bit Bit Name 15:10 OUI_LSB Default Description <0010 0000 0000 OUI Most Significant Bits: Bits 3 to 18 of the OUI (080017h) are 0000>, RO/P stored in bits 15 to 0 of this register. The most significant two bits of the OUI are ignored (the IEEE standard refers to these as bits 1 and 2). Table 10.
Table 11. Auto-Negotiation Advertisement Register (ANAR), address 0x04 Bit Bit Name Default 15 NP 0, RW Description Next Page Indication: 0 = Next Page Transfer not desired. 1 = Next Page Transfer desired. 14 RESERVED 0, RO/P 13 RF 0, RW RESERVED by IEEE: Writes ignored, Read as 0. Remote Fault: 1 = Advertises that this device has detected a Remote Fault. 0 = No Remote Fault detected.
Table 12. Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page), address 0x05 Bit Bit Name Default 15 NP 0, RO Description Next Page Indication: 0 = Link Partner does not desire Next Page Transfer. 1 = Link Partner desires Next Page Transfer. 14 ACK 0, RO Acknowledge: 1 = Link Partner acknowledges reception of the ability data word. 0 = Not acknowledged. The Device's Auto-Negotiation state machine will automatically control the this bit based on the incoming FLP bursts.
Bit Bit Name Default 15 NP 0, RO Description Next Page Indication: 1 = Link Partner desires Next Page Transfer. 0 = Link Partner does not desire Next Page Transfer. 14 ACK 0, RO Acknowledge: 1 = Link Partner acknowledges reception of the ability data word. 0 = Not acknowledged. The Device's Auto-Negotiation state machine will automatically control the this bit based on the incoming FLP bursts. Software should not attempt to write to this bit. 13 MP 0, RO Message Page: 1 = Message Page.
Table 15. Auto-Negotiation Next Page Transmit Register (ANNPTR), address 0x07 Bit Bit Name Default 15 NP 0, RW Description Next Page Indication: 0 = No other Next Page Transfer desired. 1 = Another Next Page desired. 14 RESERVED 0, RO RESERVED: Writes ignored, read as 0. 13 MP 1, RW Message Page: 1 = Message Page. 0 = Unformatted Page. 12 ACK2 0, RW Acknowledge2: 1 = Will comply with message. 0 = Cannot comply with message.
This register provides a single location within the register set for quick access to commonly accessed information. Table 16. PHY Status Register (PHYSTS), address 0x10 Bit Bit Name Default 15:14 RESERVED 0, RO 13 Receive Error Latch 0, RO/LH Description RESERVED: Write ignored, read as 0. Receive Error Latch: This bit will be cleared upon a read of the RECR register. 1 = Receive error event has occurred since last read of RXERCNT (address 0x15, Page 0). 0 = No receive error event has occurred.
DP83846A Table 16. PHY Status Register (PHYSTS), address 0x10 (Continued) Bit Bit Name Default Description 7 RESERVED 0, RO RESERVED: Writes ignored, Read as 0. 6 Remote Fault 0, RO Remote Fault: 1 = Remote Fault condition detected (cleared on read of BMSR (address 01h) register or by reset). Fault criteria: notification from Link Partner of Remote Fault via Auto-Negotiation. 0 = No remote fault condition detected.
Table 17. False Carrier Sense Counter Register (FCSCR), address 0x14 Bit Bit Name Default 15:8 RESERVED 0, RO 7:0 FCSCNT[7:0] 0, RW / COR Description RESERVED: Writes ignored, Read as 0. False Carrier Event Counter: This 8-bit counter increments on every false carrier event. This counter sticks when it reaches its max count (FFh). This counter provides information required to implement the “SymbolErrorDuringCarrier” attribute within the PHY managed object class of Clause 30 of the IEEE 802.
Bit Bit Name Default 7 Unused 0,RO 6 RESERVED 0 Description RESERVED: Must be zero. 5 FORCE_100_OK 0, RW Force 100Mb/s Good Link: 1 = Forces 100Mb/s Good Link. 0 = Normal 100Mb/s operation. 4 RESERVED 0 RESERVED: Must be zero. 3 RESERVED 0 2 NRZI_BYPASS 0, RW RESERVED: Must be zero. NRZI Bypass Enable: 1 = NRZI Bypass Enabled. 1 SCRAM_BYPASS 0, RW te 0 = NRZI Bypass Disabled. Scrambler Bypass Enable: 1 = Scrambler Bypass Enabled. 0 = Scrambler Bypass Disabled.
DP83846A Table 21. PHY Control Register (PHYCTRL), address 0x19 Bit Bit Name Default 15:12 Unused 0, RO 11 PSR_15 0, RW Description BIST Sequence select: 1 = PSR15 selected. 0 = PSR9 selected. 10 BIST_STATUS 0, RO/LL BIST Test Status: 1 = BIST pass. 0 = BIST fail. Latched, cleared by write to BIST_ START bit. 9 BIST_START 0, RW BIST Start: 1 = BIST start. 0 = BIST stop.
DP83846A Table 22. 10Base-T Status/Control Register (10BTSCR), Address 0x1A Bit Bit Name Default 15:9 Unused 0, RO 8 LOOPBACK_10_DIS 0, RW Description 10BASE-T Loopback Disable: If bit 14 (Loopback) in the BMCR is 0: 1 = 10 Mb/s Loopback is disabled. If bit 14 (Loopback) in the BMCR is 1: 1 = 10 Mb/s Loopback is enabled. 7 LP_DIS 0, RW Normal Link Pulse Disable: 1 = Transmission of NLPs is disabled. 0 = Transmission of NLPs is enabled.
Bit Bit Name Default 15 CD_ENABLE 1, RW Description CD Enable: 1 = CD Enabled - power-down mode, outputs high impedance. 0 = CD Disabled. 14 DCDCOMP 0, RW Duty Cycle Distortion Compensation: 1 = Increases the amount of DCD compensation. 13 FIL_TTL 0, RW Waveshaper Current Source Test: To check ability of waveshaper current sources to switch on/off. 1 = Test mode; waveshaping is done, but the output is a square wave. All sources are either on or off. 0 = Normal mode; sinusoidal.
Absolute Maximum Ratings Recommended Operating Conditions Supply voltage (VCC) Supply Voltage (VCC) -0.5 V to 4.2 V DC Input Voltage (VIN) -0.5V to 5.5V Ambient Temperature (TA) DC Output Voltage (VOUT) -0.5V to 5.5V Max. die temperature (Tj) Storage Temperature (TSTG) 260°C ESD Rating (RZAP = 1.5k, CZAP = 120 pF) 1.0 kV 0 to 70 °C 107°C Max case temp -65oC to 150°C Lead Temp. (TL) (Soldering, 10 sec) 3.3 Volts + 0.
Pin Types Parameter VTPTDsym TD+/− 100M Transmit Voltage Symmetry VTPTD_10 TD+/− 10M Transmit Voltage I CMOS Input Capacitance CIN1 Conditions Min 2.2 Parameter is not 100% tested Units 2.5 % 2.
DP83846A 6.1 Reset Timing VCC X1 Clock T1.0.1 T1.0.4 HARDWARE RSTN 32 CLOCKS te MDC T1.0.2 ol e Latch-In of Hardware Configuration Pins T1.0.3 INPUT OUTPUT Dual Function Pins Become Enabled As Outputs T1.0.1 T1.0.2 T1.0.
DP83846A 6.2 PGM Clock Timing X1 TX_CLK Parameter T2.0.1 te T2.0.1 Description Notes TX_CLK Duty Cycle Typ 35 Max Units 65 % Max Units 300 ns ol e 6.3 MII Serial Management Timing MDC Min T3.0.1 T3.0.4 bs MDIO (output) MDC T3.0.2 O MDIO (input) Parameter Description T3.0.3 Valid Data Notes Min Typ T3.0.1 MDC to MDIO (Output) Delay Time 0 T3.0.2 MDIO (Input) to MDC Setup Time 10 ns T3.0.3 MDIO (Input) to MDC Hold Time 10 ns T3.0.4 MDC Frequency 2.
DP83846A 6.4 100 Mb/s Timing 6.4.1 100 Mb/s MII Transmit Timing TX_CLK T4.1.2 T4.1.1 TXD[3:0] TX_EN TX_ER Parameter Valid Data Description Notes Min Typ Max Units TXD[3:0], TX_EN, TX_ER Data Setup to TX_CLK 10 ns T4.1.2 TXD[3:0], TX_EN, TX_ER Data Hold from TX_CLK 5 ns te T4.1.1 6.4.2 100 Mb/s MII Receive Timing RX_CLK ol e T4.2.1 T4.2.2 Parameter T4.2.1 Description Notes Min Typ Max Units RX_CLK Duty Cycle 35 65 % RX_CLK to RXD[3:0], RX_DV, RX_ER Delay 10 30 ns O T4.
DP83846A 6.4.3 100BASE-TX Transmit Packet Latency Timing TX_CLK TX_EN TXD IDLE TD± Parameter Description (J/K) DATA Notes TX_CLK to TD± Latency Min Typ ol e T4.3.1 te T4.3.1 Max Units 6.0 bit times Note: Latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of TX_EN to the first bit of the “J” code group as output from the TD± pins. 6.4.
DP83846A 6.4.5 100BASE-TX Transmit Timing (tR/F & Jitter) T4.5.1 +1 rise 90% 10% TD± 10% +1 fall 90% T4.5.1 -1 fall -1 rise T4.5.1 te T4.5.1 T4.5.2 TD± eye pattern T4.5.1 Description Notes Min Typ Max Units 3 4 5 ns 100 Mb/s tR and tF Mismatch 500 ps 100 Mb/s TD± Transmit Jitter 1.4 ns 100 Mb/s TD± tR and tF bs T4.5.2 ol e Parameter T4.5.2 Note1: Normal Mismatch is the difference between the maximum and minimum of all rise and fall times.
DP83846A 6.4.6 100BASE-TX Receive Packet Latency Timing RD± IDLE Data (J/K) T4.6.1 CRS T4.6.2 Parameter te RXD[3:0] RX_DV RX_ER/RXD[4] Description T4.6.1 Carrier Sense ON Delay T4.6.2 Receive Data Latency Notes Min Typ Max Units 17.5 bit times 21 bit times ol e Note: Carrier Sense On Delay is determined by measuring the time from the first bit of the “J” code group to the assertion of Carrier Sense.
DP83846A 6.5 10 Mb/s Timing 6.5.1 10 Mb/s MII Transmit Timing TX_CLK T5.1.2 T5.1.1 TXD[3:0] TX_EN Parameter Valid Data Description Notes Min Typ Max Units TXD[3:0], TX_EN Data Setup to TX_CLK 25 ns T5.1.2 TXD[3:0], TX_EN Data Hold from TX_CLK 5 ns te T5.1.1 6.5.2 10 Mb/s MII Receive Timing RX_CLK Parameter T5.2.1 Valid Data Description Notes Min Typ Max Units RX_CLK Duty Cycle 35 65 % RX_CLK to RXD[3:0], RX_DV 190 210 ns O T5.2.2 T5.2.2 bs RXD[3:0] RX_DV ol e T5.2.
DP83846A 6.5.3 10BASE-T Transmit Timing (Start of Packet) TX_CLK T5.3.1 TX_EN T5.3.2 T5.3.3 TXD[0] TPTD± Parameter te T5.3.4 Description Notes Transmit Enable Setup Time from the Falling Edge of TX_CLK T5.3.2 Transmit Data Setup Time from the Falling Edge of TX_CLK T5.3.3 Transmit Data Hold Time from the Falling Edge of TX_CLK T5.3.4 Transmit Output Delay from the Falling Edge of TX_CLK Typ Max Units 25 ns 25 ns ol e T5.3.1 Min 5 ns 6.8 bit times 6.5.
DP83846A 6.5.5 10BASE-T Receive Timing (Start of Packet) 1st SFD bit decoded 1 0 1 TPRD± T5.5.1 CRS T5.5.2 RX_CLK T5.5.4 te RXD[0] T5.5.3 Parameter ol e RX_DV Description Notes Min Typ Max Units 1 µs T5.5.1 Carrier Sense Turn On Delay (TPRD± to CRS) T5.5.2 Decoder Acquisition Time 3.6 µs T5.5.3 Receive Data Latency 17.3 bit times T5.5.
DP83846A 6.5.7 10 Mb/s Heartbeat Timing TXE TXC T5.7.2 T5.7.1 COL Parameter Description Notes Min Typ Max Units CD Heartbeat Delay 600 1600 ns T5.7.2 CD Heartbeat Duration 500 1500 ns Max Units te T5.7.1 6.5.8 10 Mb/s Jabber Timing ol e TXE T5.8.1 T5.8.2 TPTD± bs COL Parameter T5.8.1 T5.8.2 Description Notes Min Typ Jabber Activation Time 20 150 ms Jabber Deactivation Time 250 750 ms Max Units O 6.5.9 10BASE-T Normal Link Pulse Timing T5.9.2 T5.9.
DP83846A 6.5.10 Auto-Negotiation Fast Link Pulse (FLP) Timing T5.10.2 T5.10.3 T5.10.1 T5.10.1 Fast Link Pulse(s) clock pulse data pulse clock pulse T5.10.6 T5.10.5 FLP Burst Parameter Description Clock, Data Pulse Width T5.10.2 Clock Pulse to Clock Pulse Period T5.10.3 Clock Pulse to Data Pulse Period T5.10.4 Number of Pulses in a Burst T5.10.5 Burst Width T5.10.6 FLP Burst to FLP Burst Period FLP Burst Notes Min Typ Max 100 ol e T5.10.1 te T5.10.
DP83846A 6.6 Loopback Timing 6.6.1 100 Mb/s Internal Loopback Mode TX_CLK TX_EN CRS T6.1.1 RX_DV bs RXD[3:0] Parameter T6.1.1 ol e RX_CLK te TXD[3:0] Description Notes Min TX_EN to RX_DV Loopback Typ Max Units 240 ns Note1: Due to the nature of the descrambler function, all 100BASE-TX Loopback modes will cause an initial “dead-time” of up to 550 µs during which time no data will be present at the receive MII outputs.
DP83846A 6.6.2 10 Mb/s Internal Loopback Mode TX_CLK TX_EN TXD[3:0] CRS te T6.2.1 RX_DV RXD[3:0] T6.2.1 Description Notes bs Parameter ol e RX_CLK Min TX_EN to RX_DV Loopback Typ Max Units 2 µs O Note: Measurement is made from the first falling edge of TX_CLK after assertion of TX_EN. 58 www.national.
DP83846A 6.7 Isolation Timing Clear bit 10 of BMCR (return to normal operation from Isolate mode) T7.0.1 H/W or S/W Reset (with PHYAD = 00000) T7.0.2 MODE NORMAL Parameter Description From software clear of bit 10 in the BMCR register to the transition from Isolate to Normal Mode T7.0.2 From Deassertion of S/W or H/W Reset to transition from Isolate to Normal mode Notes Min Typ Max Units 100 µs 500 µs O bs ol e T7.0.1 te ISOLATE 59 www.national.
te ol e bs Plastic Quad Flat Pack (LQFP) Order Number DP83846AVHG NS Package Number VHG-80A LIFE SUPPORT POLICY O NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1.
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