DP83848C DP83848C PHYTER Commercial Temperature Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver Literature Number: SNOSAT2E
® DP83848C PHYTER - Commercial Temperature Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver General Description Features The DP83848C is a robust fully featured 10/100 single port Physical Layer device offering low power consumption, including several intelligent power down states. These low power modes increase overall product reliability due to decreased power dissipation.
DP83848C RX_CLK RXD[3:0] RX_DV RX_ER COL MDC MDIO TX_EN TX_CLK TXD[3:0] SERIAL MANAGEMENT CRS/CRS_DV MII/RMII/SNI MII/RMII/SNI INTERFACES TX_DATA RX_CLK TX_CLK MII Registers 10BASE-T & 100BASE-TX RX_DATA 10BASE-T & 100BASE-TX Auto-Negotiation State Machine Transmit Block Receive Block Clock Generation ADC DAC Auto-MDIX TD± RD± LED Drivers REFERENCE CLOCK Figure 1. DP83848C Functional Block Diagram www.national.
1.1 Serial Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 1.2 MAC Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 1.3 Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 1.4 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DP83848C 4.3 10BASE-T TRANSCEIVER MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 4.3.1 Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2 Smart Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.3 Collision Detection and SQE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10 Mb/s MII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Mb/s MII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Mb/s Serial Mode Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Mb/s Serial Mode Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DP83848C List of Figures Figure 1. DP83848C Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Figure 2. PHYAD Strapping Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 3. AN Strapping and LED Loading Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 4. Typical MDC/MDIO Read Operation . . .
Table 1. Auto-Negotiation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Table 2. PHY Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Table 3. LED Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Table 4.
DGND IOGND X1 X2 IOVDD33 MDC MDIO RESET_N LED_LINK/AN0 LED_SPEED/AN1 LED_ACT/COL/AN_EN 25MHz_OUT 36 35 34 33 32 31 30 29 28 27 26 25 37 24 RBIAS RX_CLK 38 23 PFBOUT RX_DV/MII_MODE 39 22 AVDD33 CRS/CRS_DV/LED_CFG 40 21 RESERVED RX_ER/MDIX_EN 41 20 RESERVED COL/PHYAD0 42 19 AGND RXD_0/PHYAD1 43 18 PFBIN1 RXD_1/PHYAD2 44 17 TD + RXD_2/PHYAD3 45 16 TD - RXD_3/PHYAD4 46 15 AGND IOGND 47 14 RD + IOVDD33 48 13 RD - 9 10 11 12 RESERVED RESE
The DP83848C pins are classified into the following interface categories (each interface is described in the sections that follow): All DP83848C signal pins are I/O cells regardless of the particular use. The definitions below define the functionality of the I/O cells for each pin. — Serial Management Interface — MAC Data Interface — Clock Interface — LED Interface — Reset and Power Down — Strap Options — 10/100 Mb/s PMD Interface — Special Connect Pins — Power and Ground pins Note: Strapping pin option.
DP83848C Signal Name RX_CLK Type Pin # Description O 38 MII RECEIVE CLOCK: Provides the 25 MHz recovered receive clocks for 100 Mb/s mode and 2.5 MHz for 10 Mb/s mode. Unused in RMII mode. The device uses the X1 reference clock input as the 50 MHz reference for both transmit and receive. SNI RECEIVE CLOCK: Provides the 10 MHz recovered receive clocks for 10 Mb/s SNI mode. RX_DV S, O, PD 39 MII RECEIVE DATA VALID: Asserted high to indicate that valid data is present on the corresponding RXD[3:0].
Signal Name X1 Type Pin # Description I 34 CRYSTAL/OSCILLATOR INPUT: This pin is the primary clock reference input for the DP83848C and must be connected to a 25 MHz 0.005% (+50 ppm) clock source. The DP83848C supports either an external crystal resonator connected across pins X1 and X2, or an external CMOS-level oscillator source connected to pin X1 only. RMII REFERENCE CLOCK: This pin is the primary clock reference input for the RMII mode and must be connected to a 50 MHz 0.
DP83848C 1.5 Reset and Power Down Signal Name RESET_N PWR_DOWN/INT Type Pin # Description I, PU 29 RESET: Active Low input that initializes or re-initializes the DP83848C. Asserting this pin low for at least 1 µs will force a reset process to occur. All internal registers will re-initialize to their default states as specified for each bit in the Register Block section. All strap options are re-initialized as well. I, OD, PU 7 See Section 5.5 for detailed description.
AN_EN (LED_ACT/COL) Type Pin # Description S, O, PU 26 Auto-Negotiation Enable: When high, this enables Auto-Negotiation with the capability set by ANO and AN1 pins. When low, this puts the part into Forced Mode with the capability set by AN0 and AN1 pins. AN_1 (LED_SPEED) 27 AN_0 (LED_LINK) 28 AN0 / AN1: These input pins control the forced or advertised operating mode of the DP83848C according to the following table.
DP83848C 1.7 10 Mb/s and 100 Mb/s PMD Interface Signal Name TD-, TD+ Type Pin # Description I/O 16, 17 Differential common driver transmit output (PMD Output Pair). These differential outputs are automatically configured to either 10BASE-T or 100BASE-TX signaling. In Auto-MDIX mode of operation, this pair can be used as the Receive Input pair. These pins require 3.3V bias for operation. RD-, RD+ I/O 13, 14 Differential receive input (PMD Input Pair).
VBH48A Pin # Pin Name VBH48A Pin # Pin Name 1 TX_CLK 2 TX_EN 3 TXD_0 4 TXD_1 5 TXD_2 6 TXD_3/SNI_MODE 7 PWR_DOWN/INT 8 RESERVED 9 RESERVED 10 RESERVED 11 RESERVED 12 RESERVED 13 RD - 14 RD + 15 AGND 16 TD - 17 TD + 18 PFBIN1 19 AGND 20 RESERVED 21 RESERVED 22 AVDD33 23 PFBOUT 24 RBIAS 25 25MHz_OUT 26 LED_ACT/COL/AN_EN 27 LED_SPEED/AN1 28 LED_LINK/AN0 29 RESET_N 30 MDIO 31 MDC 32 IOVDD33 33 X2 34 X1 35 IOGND 36 DGND 37 PFBIN2 38 RX_C
DP83848C 2.0 Configuration This section includes information on the various configuration options available with the DP83848C. The configuration options described below include: — — — — — — Table 1. Auto-Negotiation Modes Auto-Negotiation PHY Address and LEDs Half Duplex vs. Full Duplex Isolate mode Loopback mode BIST 2.
The Auto-Negotiation Link Partner Ability Register (ANLPAR) at address 05h is used to receive the base link code word as well as all next page code words during the negotiation. Furthermore, the ANLPAR will be updated to either 0081h or 0021h for parallel detection to either 100 Mb/s or 10 Mb/s respectively. The Auto-Negotiation Expansion Register (ANER) indicates additional Auto-Negotiation status.
The 5 PHY address inputs pins are shared with the RXD[3:0] pins and COL pin as shown below. Since the PHYAD[0] pin has weak internal pull-up resistor and PHYAD[4:1] pins have weak internal pull-down resistors, the default setting for the PHY address is 00001 (01h). Refer to Figure 2 for an example of a PHYAD connection to external components. In this example, the PHYAD strapping results in address 00011 (03h). Table 2.
The DP83848C supports three configurable Light Emitting Diode (LED) pins. The device supports three LED configurations: Link, Speed, Activity and Collision. Function are multiplexed among the LEDs. The PHY Control Register (PHYCR) for the LEDs can also be selected through address 19h, bits [6:5]. See Table 3 for LED Mode selection. Table 3.
DP83848C 2.4.2 LED Direct Control 2.6 Internal Loopback The DP83848C provides another option to directly control any or all LED outputs through the LED Direct Control Register (LEDCR), address 18h. The register does not provide read access to LEDs. The DP83848C includes a Loopback Test mode for facilitating system diagnostics. The Loopback mode is selected through bit 14 (Loopback) of the Basic Mode Control Register (BMCR).
The DP83848C supports several modes of operation using the MII interface pins. The options are defined in the following sections and include: — MII Mode — RMII Mode — 10 Mb Serial Network Interface (SNI) The modes of operation can be selected by strap options or register control. For RMII mode, it is required to use the strap option, since it requires a 50 MHz clock instead of the normal 25 MHz. In each of these modes, the IEEE 802.
DP83848C To tolerate potential frequency differences between the 50 MHz reference clock and the recovered receive clock, the receive RMII function includes a programmable elasticity buffer. The elasticity buffer is programmable to minimize propagation delay based on expected packet size and clock accuracy. This allows for supporting a range of packet sizes including jumbo frames. The elasticity buffer will force Frame Check Sequence errors for packets which overrun or underrun the FIFO.
DP83848C Table 5.
DP83848C 4.0 Architecture This section describes the operations within each transceiver module, 100BASE-TX and 10BASE-T. Each operation consists of several functional blocks and described in the following: The block diagram in Figure 6. provides an overview of each functional block within the 100BASE-TX transmit section.
DP83848C Table 6. 5.
DP83848C 4.1.1 Code-group Encoding and Injection The code-group encoder converts 4-bit (4B) nibble data generated by the MAC into 5-bit (5B) code-groups for transmission. This conversion is required to allow control data to be combined with packet data code-groups. Refer to Table 5 for 4B to 5B code-group mapping details. The code-group encoder substitutes the first 8-bits of the MAC preamble with a J/K code-group pair (11000 10001) upon transmission.
RX_CLK DP83848C RX_DV/CRS RXD[3:0] / RX_ER 4B/5B DECODER SERIAL TO PARALLEL CODE GROUP ALIGNMENT RX_DATA VALID SSD DETECT LINK INTEGRITY MONITOR DESCRAMBLER NRZI TO NRZ DECODER MLT-3 TO BINARY DECODER SIGNAL DETECT DIGITAL SIGNAL PROCESSOR ANALOG FRONT END RD +/− Figure 7. 100BASE-TX Receive Block Diagram 27 www.national.
DP83848C 4.2.2.1 Digital Adaptive Equalization and Gain Control When transmitting data at high speeds over copper twisted pair cable, frequency dependent attenuation becomes a concern. In high-speed twisted pair signalling, the frequency content of the transmitted signal can vary greatly during normal operation based primarily on the randomness of the scrambled data stream. This variation in signal attenuation caused by frequency variations must be compensated to ensure the integrity of the transmission.
DP83848C 4.2.2.2 Base Line Wander Compensation Figure 9. 100BASE-TX BLW Event The DP83848C is completely ANSI TP-PMD compliant and includes Base Line Wander (BLW) compensation. The BLW compensation block can successfully recover the TPPMD defined “killer” pattern. PMD Standard as well as the IEEE 802.3 100BASE-TX Standard for both voltage thresholds and timing parameters.
DP83848C 4.2.7 Descrambler 4.2.10 100BASE-TX Link Integrity Monitor A serial descrambler is used to de-scramble the received NRZ data. The descrambler has to generate an identical data scrambling sequence (N) in order to recover the original unscrambled data (UD) from the scrambled data (SD) as represented in the equations: The 100 Base TX Link monitor ensures that a valid and stable link is established before enabling both the Transmit and Receive PCS layer.
The smart squelch is responsible for determining when valid data is present on the differential receive inputs. The DP83848C implements an intelligent receive squelch to ensure that impulse noise on the receive inputs will not be mistaken for a valid signal. Smart squelch operation is independent of the 10BASE-T operational mode. The squelch circuitry employs a combination of amplitude and timing measurements (as specified in the IEEE 802.
DP83848C 4.3.6 Jabber Function 4.3.8 Transmit and Receive Filtering The jabber function monitors the DP83848C's output and disables the transmitter if it attempts to transmit a packet of longer than legal size. A jabber timer monitors the transmitter and disables the transmission if the transmitter is active for approximately 85 ms. External 10BASE-T filters are not required when using the DP83848C, as the required signal conditioning is integrated into the device.
DP83848C 5.0 Design Guidelines 5.1 TPI Network Circuit Figure 11 shows the recommended circuit for a 10/100 Mb/s twisted pair interface. To the right is a partial list of recommended transformers. It is important that the user realize that variations with PCB and component characteristics requires that the application be tested to ensure that the circuit meets the requirements of the intended application.
DP83848C 5.2 ESD Protection Typically, ESD precautions are predominantly in effect when handling the devices or board before being installed in a system. In those cases, strict handling procedures need be implemented during the manufacturing process to greatly reduce the occurrences of catastrophic ESD events. After the system is assembled, internal components are less sensitive from ESD events. See Section 8.0 for ESD rating.
Parameter Min Typ Frequency Max Units 50 Condition MHz Frequency +50 ppm Operational Tolerance Temperature Frequency +50 ppm Operational Temperature Rise / Fall Time 6 nsec 20% - 80% Jitter 8001 psec Short term Jitter 8001 psec Long term Stability Symmetry 1 40% 60% Duty Cycle This limit is provided as a guideline for component selection and to guaranteed by production testing.
DP83848C 5.5.2 Interrupt Mechanisms The interrupt function is controlled via register access. All interrupt sources are disabled by default. Setting bit 1 (INTEN) of MICR (0x11h) will enable interrupts to be output, dependent on the interrupt mask set in the lower byte of the MISR (0x12h). The PWR_DOWN/INT pin is asynchronously asserted low when an interrupt condition occurs. The source of the interrupt can be determined by reading the upper byte of the MISR.
The DP83848C includes an internal power-on reset (POR) function and does not need to be explicitly reset for normal operation after power up. If required during normal operation, the device can be reset by a hardware or software reset. 6.1 Hardware Reset A hardware reset is accomplished by applying a low pulse (TTL level), with a duration of at least 1 µs, to the RESET_N.
DP83848C 7.0 Register Block Table 10.
39 11h 12h 13h 14h 15h 16h MII Interrupt Control Register MII Interrupt Status and Misc.
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DP83848C 7.
DP83848C 7.1.1 Basic Mode Control Register (BMCR) Table 12. Basic Mode Control Register (BMCR), address 0x00 Bit Bit Name Default 15 Reset 0, RW/SC Description Reset: 1 = Initiate software Reset / Reset in Process. 0 = Normal operation. This bit, which is self-clearing, returns a value of one until the reset process is complete. The configuration is re-strapped. 14 Loopback 0, RW Loopback: 1 = Loopback enabled. 0 = Normal operation.
DP83848C Table 12. Basic Mode Control Register (BMCR), address 0x00 (Continued) Bit Bit Name Default 7 Collision Test 0, RW Description Collision Test: 1 = Collision test enabled. 0 = Normal operation. When set, this bit will cause the COL signal to be asserted in response to the assertion of TX_EN within 512-bit times. The COL signal will be de-asserted within 4-bit times in response to the de-assertion of TX_EN. 6:0 RESERVED 0, RO RESERVED: Write ignored, read as 0. 43 www.national.
DP83848C 7.1.2 Basic Mode Status Register (BMSR) Table 13. Basic Mode Status Register (BMSR), address 0x01 Bit Bit Name Default 15 100BASE-T4 0, RO/P 14 100BASE-TX 1, RO/P Description 100BASE-T4 Capable: 0 = Device not able to perform 100BASE-T4 mode. Full Duplex 13 100BASE-TX 1 = Device able to perform 100BASE-TX in full duplex mode. 1, RO/P Half Duplex 12 10BASE-T 100BASE-TX Full Duplex Capable: 100BASE-TX Half Duplex Capable: 1 = Device able to perform 100BASE-TX in half duplex mode.
7.1.3 PHY Identifier Register #1 (PHYIDR1) Table 14. PHY Identifier Register #1 (PHYIDR1), address 0x02 Bit Bit Name 15:0 OUI_MSB Default Description <0010 0000 0000 OUI Most Significant Bits: Bits 3 to 18 of the OUI (080017h) are 0000>, RO/P stored in bits 15 to 0 of this register. The most significant two bits of the OUI are ignored (the IEEE standard refers to these as bits 1 and 2). 7.1.4 PHY Identifier Register #2 (PHYIDR2) Table 15.
DP83848C Table 16. Negotiation Advertisement Register (ANAR), address 0x04 (Continued) Bit Bit Name Default 11 ASM_DIR 0, RW Description Asymmetric PAUSE Support for Full Duplex Links: The ASM_DIR bit indicates that asymmetric PAUSE is supported. Encoding and resolution of PAUSE bits is defined in IEEE 802.3 Annex 28B, Tables 28B-2 and 28B-3, respectively. Pause resolution status is reported in PHYCR[13:12].
This register contains the advertised abilities of the Link Partner as received during Auto-Negotiation. The content changes after the successful auto-negotiation if Next-pages are supported. Table 17. Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page), address 0x05 Bit Bit Name Default 15 NP 0, RO Description Next Page Indication: 0 = Link Partner does not desire Next Page Transfer. 1 = Link Partner desires Next Page Transfer.
DP83848C 7.1.7 Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page) Table 18. Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page), address 0x05 Bit Bit Name Default 15 NP 0, RO Description Next Page Indication: 1 = Link Partner desires Next Page Transfer. 0 = Link Partner does not desire Next Page Transfer. 14 ACK 0, RO Acknowledge: 1 = Link Partner acknowledges reception of the ability data word. 0 = Not acknowledged.
Bit Bit Name Default 0 LP_AN_ABLE 0, RO Description Link Partner Auto-Negotiation Able: 1 = indicates that the Link Partner supports Auto-Negotiation. 0 = indicates that the Link Partner does not support Auto-Negotiation. 7.1.9 Auto-Negotiation Next Page Transmit Register (ANNPTR) This register contains the next page information sent by this device to its Link Partner during Auto-Negotiation. Table 20.
DP83848C 7.2 Extended Registers 7.2.1 PHY Status Register (PHYSTS) This register provides a single location within the register set for quick access to commonly accessed information. Table 21. PHY Status Register (PHYSTS), address 0x10 Bit Bit Name Default Description 15 RESERVED 0, RO RESERVED: Write ignored, read as 0. 14 MDI-X mode 0, RO MDI-X mode as reported by the Auto-Negotiation logic: This bit will be affected by the settings of the MDIX_EN and FORCE_MDIX bits in the PHYCR register.
Bit Bit Name Default 5 Jabber Detect 0, RO Description Jabber Detect: This bit only has meaning in 10 Mb/s mode This bit is a duplicate of the Jabber Detect bit in the BMSR register, except that it is not cleared upon a read of the PHYSTS register. 1 = Jabber condition detected. 0 = No Jabber. 4 Auto-Neg Complete 0, RO Auto-Negotiation Complete: 1 = Auto-Negotiation complete. 0 = Auto-Negotiation not complete. 3 Loopback Status 0, RO Loopback: 1 = Loopback enabled. 0 = Normal operation.
DP83848C 7.2.2 MII Interrupt Control Register (MICR) This register implements the MII Interrupt PHY Specific Control register. Sources for interrupt generation include: Energy Detect State Change, Link State Change, Speed Status Change, Duplex Status Change, Auto-Negotiation Complete or any of the counters becoming half-full. The individual interrupt events must be enabled by setting bits in the MII Interrupt Status and Event Control Register (MISR). Table 22.
This register contains event status and enables for the interrupt function. If an event has occurred since the last read of this register, the corresponding status bit will be set. If the corresponding enable bit in the register is set, an interrupt will be generated if the event occurs. The MICR register controls must also be set to allow interrupts. The status indications in this register will be set even if the interrupt is not enabled Table 23. MII Interrupt Status and Misc.
DP83848C 7.2.4 False Carrier Sense Counter Register (FCSCR) This counter provides information required to implement the “False Carriers” attribute within the MAU managed object class of Clause 30 of the IEEE 802.3u specification. Table 24.
DP83848C 7.2.6 100 Mb/s PCS Configuration and Status Register (PCSR) Table 26. 100 Mb/s PCS Configuration and Status Register (PCSR), address 0x16 Bit Bit Name Default 15:13 RESERVED <00>, RO 12 RESERVED 0 Description RESERVED: Writes ignored, Read as 0. RESERVED: Must be zero. 11 RESERVED 0 10 TQ_EN 0, RW RESERVED: Must be zero. 100Mbs True Quiet Mode Enable: 1 = Transmit True Quiet Mode. 0 = Normal Transmit Mode.
DP83848C 7.2.7 RMII and Bypass Register (RBR) This register configures the RMII Mode of operation. When RMII mode is disabled, the RMII functionality is bypassed. Table 27. RMII and Bypass Register (RBR), addresses 0x17 Bit Bit Name Default 15:6 RESERVED 0, RO 5 RMII_MODE Strap, RW Description RESERVED: Writes ignored, read as 0. Reduced MII Mode: 0 = Standard MII Mode 1 = Reduced MII Mode 4 RMII_REV1_0 0, RW Reduce MII Revision 1.0: 0 = (RMII revision 1.
DP83848C 7.2.9 PHY Control Register (PHYCR) Table 29. PHY Control Register (PHYCR), address 0x19 Bit Bit Name Default 15 MDIX_EN Strap, RW Description Auto-MDIX Enable: 1 = Enable Auto-neg Auto-MDIX capability. 0 = Disable Auto-neg Auto-MDIX capability. The Auto-MDIX algorithm requires that the Auto-Negotiation Enable bit in the BMCR register to be set. If Auto-Negotiation is not enabled, Auto-MDIX should be disabled as well. 14 FORCE_MDIX 0, RW Force MDIX: 1 = Force MDI pairs to cross.
DP83848C Table 29.
DP83848C Table 30. 10Base-T Status/Control Register (10BTSCR), address 0x1A Bit Bit Name Default 7 LP_DIS 0, RW Description Normal Link Pulse Disable: 1 = Transmission of NLPs is disabled. 0 = Transmission of NLPs is enabled. 6 FORCE_LINK_10 0, RW Force 10Mb Good Link: 1 = Forced Good 10Mb Link. 0 = Normal Link Status. 5 RESERVED 0, RW RESERVED: Must be zero. 4 POLARITY RO/LH 10Mb Polarity Status: This bit is a duplication of bit 12 in the PHYSTS register.
DP83848C 7.2.11 CD Test and BIST Extensions Register (CDCTRL1) Table 31. CD Test and BIST Extensions Register (CDCTRL1), address 0x1B Bit Bit Name Default 15:8 BIST_ERROR_CO UNT 0, RO RESERVED 0, RW 7:6 Description BIST ERROR Counter: Counts number of errored data nibbles during Packet BIST. This value will reset when Packet BIST is restarted. The counter sticks when it reaches its max count. RESERVED: Must be zero.
DP83848C 7.2.12 Energy Detect Control (EDCR) Table 32. Energy Detect Control (EDCR), address 0x1D Bit Bit Name Default 15 ED_EN 0, RW Description Energy Detect Enable: Allow Energy Detect Mode. When Energy Detect is enabled and Auto-Negotiation is disabled via the BMCR register, Auto-MDIX should be disabled via the PHYCR register. 14 ED_AUTO_UP 1, RW Energy Detect Automatic Power Up: Automatically begin power up sequence when Energy Detect Data Threshold value (EDCR[3:0]) is reached.
DP83848C 8.0 Electrical Specifications Note: All parameters are guaranteed by test, statistical analysis or design. Absolute Maximum Ratings Recommended Operating Conditions Supply Voltage (VCC) Supply voltage (VCC) -0.5 V to 4.2 V 3.3 Volts + .3V DC Input Voltage (VIN) -0.5V to VCC + 0.5V Commercial - Ambient Temperature (TA) DC Output Voltage (VOUT) -0.5V to VCC + 0.5V Power Dissipation (PD) Storage Temperature (TSTG) 92 °C Max. die temperature (Tj) 150 °C Lead Temp.
Pin Types Parameter Conditions Min Typ Max SDTHoff PMD Input Pair 100BASE-TX Signal detect turnoff threshold VTH1 PMD Input Pair 10BASE-T Receive Threshold Idd100 Supply 100BASE-TX (Full Duplex) 81 mA Idd10 Supply 10BASE-T (Full Duplex) 92 mA Idd Supply Power Down Mode 14 mA 200 mV diff pk-pk 585 63 Units mV www.national.
DP83848C 8.2 AC Specs 8.2.1 Power Up Timing Vcc X1 clock T2.1.1 Hardware RESET_N 32 clocks MDC T2.1.2 Latch-In of Hardware Configuration Pins T2.1.3 input Dual Function Pins Become Enabled As Outputs Parameter Description output Notes Min Typ Max Units T2.1.1 Post Power Up Stabilization MDIO is pulled high for 32-bit serial mantime prior to MDC preamble for agement initialization register accesses X1 Clock must be stable for a min. of 167ms at power up. 167 ms T2.1.
DP83848C 8.2.2 Reset Timing Vcc X1 clock T2.2.1 T2.2.4 Hardware RESET_N 32 clocks MDC T2.2.2 Latch-In of Hardware Configuration Pins T2.2.3 input Dual Function Pins Become Enabled As Outputs Parameter Description output Notes Min Typ Max Units T2.2.1 Post RESET Stabilization time MDIO is pulled high for 32-bit serial manprior to MDC preamble for reg- agement initialization ister accesses 3 µs T2.2.
DP83848C 8.2.3 MII Serial Management Timing MDC T2.3.1 T2.3.4 MDIO (output) MDC T2.3.2 Valid Data MDIO (input) Parameter T2.3.3 Description Notes Min Typ Max Units 30 ns T2.3.1 MDC to MDIO (Output) Delay Time 0 T2.3.2 MDIO (Input) to MDC Setup Time 10 ns T2.3.3 MDIO (Input) to MDC Hold Time 10 ns T2.3.4 MDC Frequency 2.5 25 MHz 8.2.4 100 Mb/s MII Transmit Timing T2.4.1 T2.4.1 TX_CLK T2.4.3 T2.4.2 TXD[3:0] TX_EN Parameter Valid Data Min Typ T2.4.
DP83848C 8.2.5 100 Mb/s MII Receive Timing T2.5.1 T2.5.1 RX_CLK T2.5.2 RXD[3:0] RX_DV RX_ER Valid Data Parameter Description Notes Min Typ Max Units 20 24 ns 30 ns T2.5.1 RX_CLK High/Low Time 100 Mb/s Normal mode 16 T2.5.2 RX_CLK to RXD[3:0], RX_DV, RX_ER Delay 100 Mb/s Normal mode 10 Note: RX_CLK may be held low or high for a longer period of time during transition between reference and recovered clocks. Minimum high and low times will not be violated. 8.2.
DP83848C 8.2.7 100BASE-TX Transmit Packet Deassertion Timing TX_CLK TX_EN TXD T2.7.1 PMD Output Pair Parameter T2.7.1 DATA DATA (T/R) (T/R) Description TX_CLK to PMD Output Pair Deassertion Notes 100 Mb/s Normal mode IDLE IDLE Min Typ 6 Max Units bits Note: Deassertion is determined by measuring the time from the first rising edge of TX_CLK occurring after the deassertion of TX_EN to the first bit of the “T” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100 Mb/s mode.
DP83848C 8.2.8 100BASE-TX Transmit Timing (tR/F & Jitter) T2.8.1 +1 rise 90% 10% PMD Output Pair 10% +1 fall 90% T2.8.1 -1 fall -1 rise T2.8.1 T2.8.1 T2.8.2 PMD Output Pair eye pattern Parameter T2.8.1 T2.8.2 T2.8.2 Description Notes Min Typ Max Units 3 4 5 ns 100 Mb/s tR and tF Mismatch 500 ps 100 Mb/s PMD Output Pair Transmit Jitter 1.
DP83848C 8.2.9 100BASE-TX Receive Packet Latency Timing PMD Input Pair IDLE Data (J/K) T2.9.1 CRS T2.9.2 RXD[3:0] RX_DV RX_ER Parameter Description Notes Min Typ Max Units T2.9.1 Carrier Sense ON Delay 100 Mb/s Normal mode 20 bits T2.9.2 Receive Data Latency 100 Mb/s Normal mode 24 bits Note: Carrier Sense On Delay is determined by measuring the time from the first bit of the “J” code group to the assertion of Carrier Sense.
DP83848C 8.2.11 10 Mb/s MII Transmit Timing T2.11.1 T2.11.1 TX_CLK T2.11.3 T2.11.2 TXD[3:0] TX_EN Parameter Valid Data Description Notes Min Typ Max Units 200 210 T2.11.1 TX_CLK High/Low Time 10 Mb/s MII mode 190 ns T2.11.2 TXD[3:0], TX_EN Data Setup to TX_CLK fall 10 Mb/s MII mode 25 ns T2.11.3 TXD[3:0], TX_EN Data Hold from TX_CLK rise 10 Mb/s MII mode 0 ns Note: An attached Mac should drive the transmit signals using the positive edge of TX_CLK.
DP83848C 8.2.13 10 Mb/s Serial Mode Transmit Timing T2.13.2 T2.13.1 TX_CLK T2.13.4 T2.13.3 TXD[0] TX_EN Parameter Valid Data Description Notes Min Typ Max Units T2.13.1 TX_CLK High Time 10 Mb/s Serial mode 20 25 30 ns T2.13.2 TX_CLK Low Time 10 Mb/s Serial mode 70 75 80 ns T2.13.3 TXD_0, TX_EN Data Setup to TX_CLK rise 10 Mb/s Serial mode 25 ns T2.13.4 TXD_0, TX_EN Data Hold from TX_CLK rise 10 Mb/s Serial mode 0 ns 8.2.14 10 Mb/s Serial Mode Receive Timing T2.14.1 T2.
DP83848C 8.2.15 10BASE-T Transmit Timing (Start of Packet) TX_CLK TX_EN TXD T2.15.2 PMD Output Pair T2.15.1 Parameter T2.15.1 Description Notes Transmit Output Delay from the Min Typ Max Units 10 Mb/s MII mode 3.5 bits 10 Mb/s Serial mode 3.5 bits Falling Edge of TX_CLK T2.15.2 Transmit Output Delay from the Rising Edge of TX_CLK Note: 1 bit time = 100 ns in 10Mb/s. 8.2.16 10BASE-T Transmit Timing (End of Packet) TX_CLK TX_EN 0 PMD Output Pair T2.16.1 0 T2.16.
DP83848C 8.2.17 10BASE-T Receive Timing (Start of Packet) 1st SFD bit decoded 1 0 1 0 1 0 1 0 1 0 1 1 TPRD± T2.17.1 CRS RX_CLK T2.17.2 RX_DV T2.17.3 0000 RXD[3:0] Parameter Preamble Description SFD Notes Min Data Typ Max Units 1000 ns T2.17.1 Carrier Sense Turn On Delay (PMD Input Pair to CRS) 630 T2.17.2 RX_DV Latency 10 bits T2.17.
DP83848C 8.2.19 10 Mb/s Heartbeat Timing TX_EN TX_CLK T2.19.2 T2.19.1 COL Parameter Description Notes Min Typ Max Units T2.19.1 CD Heartbeat Delay All 10 Mb/s modes 1200 ns T2.19.2 CD Heartbeat Duration All 10 Mb/s modes 1000 ns 8.2.20 10 Mb/s Jabber Timing TXE T2.20.1 T2.20.2 PMD Output Pair COL Parameter Description Notes Min Typ Max Units T2.20.1 Jabber Activation Time 85 ms T2.20.2 Jabber Deactivation Time 500 ms 75 www.national.
DP83848C 8.2.21 10BASE-T Normal Link Pulse Timing T2.21.2 T2.21.1 Normal Link Pulse(s) Parameter Description Notes Min Typ Max Units T2.21.1 Pulse Width 100 ns T2.21.2 Pulse Period 16 ms Note: These specifications represent transmit timings. 8.2.22 Auto-Negotiation Fast Link Pulse (FLP) Timing T2.22.2 T2.22.3 T2.22.1 T2.22.1 Fast Link Pulse(s) clock pulse data pulse clock pulse T2.22.5 T2.22.4 FLP Burst Parameter FLP Burst Description Notes Min Typ Max Units T2.22.
DP83848C 8.2.23 100BASE-TX Signal Detect Timing PMD Input Pair T2.23.1 T2.23.2 SD+ internal Parameter Description Notes Min Typ Max Units T2.23.1 SD Internal Turn-on Time 1 ms T2.23.2 SD Internal Turn-off Time 350 µs Max Units 240 ns Note: The signal amplitude on PMD Input Pair must be TP-PMD compliant. 8.2.24 100 Mb/s Internal Loopback Timing TX_CLK TX_EN TXD[3:0] CRS T2.24.1 RX_CLK RX_DV RXD[3:0] Parameter T2.24.
DP83848C 8.2.25 10 Mb/s Internal Loopback Timing TX_CLK TX_EN TXD[3:0] CRS T2.25.1 RX_CLK RX_DV RXD[3:0] Parameter T2.25.1 Description TX_EN to RX_DV Loopback Notes Min 10 Mb/s internal loopback mode Note: Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN. www.national.
DP83848C 8.2.26 RMII Transmit Timing T2.26.1 X1 T2.26.2 TXD[1:0] TX_EN T2.26.3 Valid Data T2.26.4 PMD Output Pair Parameter Symbol Description Notes Min 50 MHz Reference Clock Typ T2.26.1 X1 Clock Period T2.26.2 TXD[1:0], TX_EN, Data Setup to X1 rising 4 ns T2.26.3 TXD[1:0], TX_EN, Data Hold from X1 rising 2 ns T2.26.4 X1 Clock to PMD Output Pair From X1 Rising edge to first bit of symbol Latency 79 20 Max Units 17 ns bits www.national.
DP83848C 8.2.27 RMII Receive Timing PMD Input Pair IDLE (J/K) Data Data (TR) T2.27.4 T2.27.5 X1 T2.27.1 T2.27.2 T2.27.3 T2.27.2 T2.27.2 RX_DV CRS_DV T2.27.2 RXD[1:0] RX_ER Parameter Description Notes Min 50 MHz Reference Clock Typ Max 20 Units T2.27.1 X1 Clock Period T2.27.2 RXD[1:0], CRS_DV, RX_DV, and RX_ER output delay from X1 rising T2.27.3 CRS ON delay From JK symbol on PMD Receive Pair to initial assertion of CRS_DV 18.5 bits T2.27.
DP83848C 8.2.28 Isolation Timing Clear bit 10 of BMCR (return to normal operation from Isolate mode) T2.28.1 H/W or S/W Reset (with PHYAD = 00000) T2.28.2 MODE NORMAL ISOLATE Max Units T2.28.1 Parameter From software clear of bit 10 in the BMCR register to the transition from Isolate to Normal Mode Description Notes Min Typ 100 µs T2.28.2 From Deassertion of S/W or H/W Reset to transition from Isolate to Normal mode 500 µs Max Units 8.2.29 25 MHz_OUT Timing X1 T2.29.2 T2.29.1 T2.29.
DP83848C 8.2.30 100 Mb/s X1 to TX_CLK Timing X1 T2.30.1 TX_CLK Parameter T2.30.1 Description Notes X1 to TX_CLK delay 100 Mb/s Normal mode Min 0 Typ Max Units 5 ns Note: X1 to TX_CLK timing is provided to support devices that use X1 instead of TX_CLK as the reference for transmit Mll data. www.national.
DP83848C Notes: 83 www.national.
DP83848C PHYTER® — Commercial Temperature Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver 9.0 Physical Dimensions inches (millimeters) unless otherwise noted Lead Quad Frame Package (LQFP) NS Package Number VBH48A THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PROCUCTS.
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