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DP83848J

DP83848J PHYTER Mini LS Commercial Temperature Single Port 10/100 Mb/s

Ethernet Transceiver

Literature Number: SNLS250D

Summary of content (80 pages)

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DP83848J DP83848J PHYTER Mini LS Commercial Temperature Single Port 10/100 Mb/s Ethernet Transceiver Literature Number: SNLS250D
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DP83848J PHYTER® Mini LS Commercial Temperature Single Port 10/100 Ethernet Transceiver General Description Features The DP83848J addresses the quality, reliability and small • Low-power 3.3V, 0.18µm CMOS technology form factor required for space sensitive applications in • Auto-MDIX for 10/100 Mb/s embedded systems. • Energy Detection Mode The DP83848J offers performance far exceeding the • 3.
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DP83848J RX_CLK RXD[3:0] RX_DV RX_ER COL MDC MDIO TX_EN TX_CLK TXD[3:0] SERIAL MANAGEMENT CRS/CRS_DV MII/RMII MII/RMII INTERFACE TX_DATA RX_CLK TX_CLK RX_DATA MII Registers 10BASE-T & 100BASE-TX 10BASE-T & 100BASE-TX Auto-Negotiation State Machine Transmit Block Receive Block Clock Generation ADC DAC Auto-MDIX TD± RD± LED Driver REFERENCE CLOCK Figure 1. DP83848J Functional Block Diagram www.national.
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1.0 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 Serial Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 1.2 MAC Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 1.3 Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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DP83848J 4.2.10 100BASE-TX Link Integrity Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.2.11 Bad SSD Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.3 10BASE-T TRANSCEIVER MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.3.1 Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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10BASE-T Transmit Timing (Start of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10BASE-T Transmit Timing (End of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10BASE-T Receive Timing (Start of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10BASE-T Receive Timing (End of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Mb/s Heartbeat Timing . . . . . . . . . . . . . . . . .
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DP83848J List of Figures Figure 1. DP83848J Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Figure 2. PHYAD Strapping Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 3. AN Strapping and LED Loading Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 4. Typical MDC/MDIO Read Operation . . . . . . . . . . . . . . . . . . . . . . . . .
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Table 1. Auto-Negotiation Modes in DP83848J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 2. PHY Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 3. LED Mode Select for DP83848J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 4. Supported packet sizes at +/-50ppm +/-100ppm for each clock . . . . . . . . . . . . . . . . . . .
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DP83848J Pin Layout for DP83848J RX_CLK 31 RX_DV/MII_MODE 32 CRS/CRS_DV/LED_CFG 33 RX_ER/MDIX_EN 34 COL/PHYAD0 35 RXD_0/PHYAD1 36 RXD_1/PHYAD2 37 RXD_2/PHYAD3 38 RXD_3/PHYAD4 39 IOGND 40 IOVDD33 1 30 PFBIN2 TX_CLK 2 29 DGND TX_EN 3 28 X1 TXD_0 4 27 X2 TXD_1 5 TXD_2 6 TXD_3 7 24 MDIO RESERVED 8 23 RESET_N RESERVED 9 RESERVED 10 26 IOVDD33 DP83848J 25 MDC 22 LED_LINK/AN0 DAP 21 LED_SPEED/AN1 20 RBIAS 19 PFBOUT 18 AVDD33 17 AGND 16 PFBIN1 15 TD + 14 TD - 13 AGN
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The DP83848J pins are classified into the following interface categories (each interface is described in the sections that follow): Note: Strapping pin option. Please see Section 1.6 for strap definitions. — — — — — — — — — Type: I Type: O Type: I/O Type: PD,PU Type: S All DP83848J signal pins are I/O cells regardless of the particular use. The definitions below define the functionality of the I/O cells for each pin.
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DP83848J Signal Name RX_ER Type Pin # Description S, O, PU 34 MII RECEIVE ERROR: Asserted high synchronously to RX_CLK to indicate that an invalid symbol has been detected within a received packet in 100 Mb/s mode. RMII RECEIVE ERROR: Assert high synchronously to X1 whenever it detects a media error and RX_DV is asserted in 100 Mb/s mode. This pin is not required to be used by a MAC, in either MII or RMII mode, since the Phy is required to corrupt data on a receive error.
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DP83848J 1.4 LED INTERFACE See Table 3 for LED Mode Selection. Signal Name LED_LINK Type Pin # Description S, O, PU 22 LINK LED: In Mode 1, this pin indicates the status of the LINK. The LED will be ON when Link is good. LINK/ACT LED: In Mode 2, this pin indicates transmit and receive activity in addition to the status of the Link. The LED will be ON when Link is good. It will blink when the transmitter or receiver is active.
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DP83848J Signal Name Type Pin # Description AN0 (LED_LINK) S, O, PU 22 AN1 (LED_SPEED) S, O, PU 21 These input pins control the advertised operating mode of the device according to the following table. The value on these pins are set by connecting them to GND (0) or VCC (1) through 2.2 kΩ resistors. These pins should NEVER be connected directly to GND or VCC. The value set at this input is latched into the DP83848J at Hardware-Reset.
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Signal Name TD-, TD+ Type Pin # Description I/O 14, 15 Differential common driver transmit output (PMD Output Pair). These differential outputs are automatically configured to either 10BASE-T or 100BASE-TX signaling. In Auto-MDIX mode of operation, this pair can be used as the Receive Input pair. These pins require 3.3V bias for operation. RD-, RD+ I/O 11, 12 Differential receive input (PMD Input Pair).
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DP83848J 1.
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This section includes information on the various configuration options available with the DP83848J. The configuration options described below include: — — — — — — Auto-Negotiation PHY Address and LED Half Duplex vs. Full Duplex Isolate mode Loopback mode BIST 2.1.2 Auto-Negotiation Register Control When Auto-Negotiation is enabled, the DP83848J transmits the abilities programmed into the Auto-Negotiation Advertisement register (ANAR) at address 04h via FLP Bursts.
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DP83848J 2.1.3 Auto-Negotiation Parallel Detection Auto-MDIX is enabled by default and can be configured via strap or via PHYCR (0x19h) register, bits [15:14]. The DP83848J supports the Parallel Detection function as defined in the IEEE 802.3u specification. Parallel Detection requires both the 10 Mb/s and 100 Mb/s receivers to monitor the receive signal and report link status to the Auto-Negotiation function.
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The 5 PHY address inputs pins are shared with the RXD[3:0] pins and COL pin as shown below. Refer to Figure 2 for an example of a PHYAD connection to external components. In this example, the PHYAD strapping results in address 00011 (03h). Table 2. PHY Address Mapping Pin # PHYAD Function Since the PHYAD[0] pin has weak internal pull-up resistor and PHYAD[4:1] pins have weak internal pull-down resistors, the default setting for the PHY address is 00001 (01h).
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sults in Auto-Negotiation with 10BASE-T Half-Duplex , 100BASE-TX, Half-Duplex advertised. The DP83848J supports configurable Light Emitting Diode (LED) pins for configuring the link and speed. The PHY Control Register (PHYCR) for the LED can also be selected through address 19h, bit [5]. The adaptive nature of the LED output helps to simplify potential implementation issues of this dual purpose pin. .
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The DP83848J supports both half and full duplex operation at both 10 Mb/s and 100 Mb/s speeds. Half-duplex relies on the CSMA/CD protocol to handle collisions and network access. In Half-Duplex mode, CRS responds to both transmit and receive activity in order to maintain compliance with the IEEE 802.3 specification.
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DP83848J 3.0 Functional Description active simultaneously. Collisions are reported by the COL signal on the MII. The DP83848J supports two modes of operation using the MII interface pins. The options are defined in the following sections and include: If the DP83848J is transmitting in 10 Mb/s mode when a collision is detected, the collision is not reported until seven bits have been received while in the collision state. This prevents a collision being reported incorrectly due to noise on the network.
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The elasticity buffer will force Frame Check Sequence errors for packets which overrun or underrun the FIFO. To tolerate potential frequency differences between the 50 Underrun and Overrun conditions can be reported in the MHz reference clock and the recovered receive clock, the RMII and Bypass Register (RBR). The following table indireceive RMII function includes a programmable elasticity cates how to program the elasticity buffer fifo (in 4-bit increbuffer.
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DP83848J MDC MDIO Z Z (STA) Z MDIO Z (PHY) Z 0 1 1 0 0 1 1 0 0 0 0 0 0 0 Idle Start Opcode (Read) PHY Address (PHYAD = 0Ch) Register Address (00h = BMCR) Z 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 TA Register Data Z Idle Figure 4. Typical MDC/MDIO Read Operation MDC MDIO Z Z (STA) Z Idle 0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Start Opcode (Write) PHY Address (PHYAD = 0Ch) Register Address (00h = BMCR) TA Figure 5. Typical MDC/MDIO Write Operation 3.3.
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The block diagram in Figure 6. provides an overview of each functional block within the 100BASE-TX transmit secThis section describes the operations within each trans- tion. ceiver module, 100BASE-TX and 10BASE-T. Each operation consists of several functional blocks and described in The Transmitter section consists of the following functional blocks: the following: — 100BASE-TX Transmitter — 100BASE-TX Receiver — 10BASE-T Transceiver Module 4.
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DP83848J Table 6.
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The code-group encoder converts 4-bit (4B) nibble data generated by the MAC into 5-bit (5B) code-groups for transmission. This conversion is required to allow control data to be combined with packet data code-groups. Refer to for 4B to 5B code-group mapping details. The code-group encoder substitutes the first 8-bits of the MAC preamble with a J/K code-group pair (11000 10001) upon transmission.
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DP83848J RX_DV/CRS RX_CLK RXD[3:0] / RX_ER 4B/5B DECODER SERIAL TO PARALLEL CODE GROUP ALIGNMENT RX_DATA VALID SSD DETECT LINK INTEGRITY MONITOR DESCRAMBLER NRZI TO NRZ DECODER MLT-3 TO BINARY DECODER DIGITAL SIGNAL PROCESSOR ANALOG FRONT END RD +/− Figure 7. 100BASE-TX Receive Block Diagram www.national.
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When transmitting data at high speeds over copper twisted pair cable, frequency dependent attenuation becomes a concern. In high-speed twisted pair signalling, the frequency content of the transmitted signal can vary greatly during normal operation based primarily on the randomness of the scrambled data stream. This variation in signal attenuation caused by frequency variations must be compensated to ensure the integrity of the transmission.
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DP83848J 4.2.2.2 Base Line Wander Compensation Figure 9. 100BASE-TX BLW Event The DP83848J is completely ANSI TP-PMD compliant and includes Base Line Wander (BLW) compensation. The BLW compensation block can successfully recover the TP-PMD defined “killer” pattern. 4.2.4 MLT-3 to NRZI Decoder The DP83848J decodes the MLT-3 information from the Digital Adaptive Equalizer block to binary NRZI data.
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A serial descrambler is used to de-scramble the received NRZ data. The descrambler has to generate an identical data scrambling sequence (N) in order to recover the original unscrambled data (UD) from the scrambled data (SD) as represented in the equations: SD = ( UD ⊕ N ) UD = ( SD ⊕ N ) Synchronization of the descrambler to the original scrambling sequence (N) is achieved based on the knowledge that the incoming scrambled data stream consists of scrambled IDLE data.
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DP83848J 4.3.2 Smart Squelch within 150 ns. Finally the signal must again exceed the original squelch level within a 150 ns to ensure that the input waveform will not be rejected. This checking procedure results in the loss of typically three preamble bits at the beginning of each packet. The smart squelch is responsible for determining when valid data is present on the differential receive inputs.
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4.3.8 Transmit and Receive Filtering The jabber function monitors the DP83848J's output and disables the transmitter if it attempts to transmit a packet of longer than legal size. A jabber timer monitors the transmitter and disables the transmission if the transmitter is active for approximately 85 ms. External 10BASE-T filters are not required when using the DP83848J, as the required signal conditioning is integrated into the device.
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DP83848J 5.0 Design Guidelines 5.1 TPI NETWORK CIRCUIT Pulse H1102 Pulse H2019 Pulse J0011D21 Pulse J0011D21B Figure 11 shows the recommended circuit for a 10/100 Mb/s twisted pair interface. To the right is a partial list of recommended transformers. It is important that the user realize that variations with PCB and component characteristics requires that the application be tested to ensure that the circuit meets the requirements of the intended application.
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Typically, ESD precautions are predominantly in effect when handling the devices or board before being installed in a system. In those cases, strict handling procedures need be implemented during the manufacturing process to greatly reduce the occurrences of catastrophic ESD events. After the system is assembled, internal components are less sensitive from ESD events. See Section 8.0 for ESD rating. capacitor values will vary with the crystal vendors; check with the vendor for the recommended loads.
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DP83848J Table 8. 50 MHz Oscillator Specification Parameter Min Frequency Typ Max 25 Units Condition MHz +50 ppm Operational Temperature +50 ppm 1 year aging Rise / Fall Time 6 nsec 20% - 80% Jitter 8001 psec Short term Jitter 8001 psec Long term Frequency Tolerance Frequency Stability Symmetry 40% 60% Duty Cycle 1. This limit is provided as a guideline for component selection and not guaranteed by production testing.
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5.6 ENERGY DETECT MODE To ensure correct operation for the DP83848J, parallel caps with values of 10 µF (Tantalum) and 0.1 µF should be placed close to pin 19 (PFBOUT) of the device. When Energy Detect is enabled and there is no activity on the cable, the DP83848J will remain in a low power mode while monitoring the transmission line. Activity on the line will cause the DP83848J to go through a normal power up sequence.
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DP83848J 7.0 Register Block Table 10.
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DP83848J 7.
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DP83848J 7.1.1 Basic Mode Control Register (BMCR) Table 12. Basic Mode Control Register (BMCR), address 0x00 Bit Bit Name Default 15 Reset 0, RW/SC Description Reset: 1 = Initiate software Reset / Reset in Process. 0 = Normal operation. This bit, which is self-clearing, returns a value of one until the reset process is complete. The configuration is re-strapped. 14 Loopback 0, RW Loopback: 1 = Loopback enabled. 0 = Normal operation.
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DP83848J Table 12. Basic Mode Control Register (BMCR), address 0x00 (Continued) Bit Bit Name Default 7 Collision Test 0, RW Description Collision Test: 1 = Collision test enabled. 0 = Normal operation. When set, this bit will cause the COL signal to be asserted in response to the assertion of TX_EN within 512-bit times. The COL signal will be de-asserted within 4-bit times in response to the de-assertion of TX_EN. 6:0 RESERVED 0, RO RESERVED: Write ignored, read as 0. 41 www.national.
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DP83848J 7.1.2 Basic Mode Status Register (BMSR) Table 13. Basic Mode Status Register (BMSR), address 0x01 Bit Bit Name Default 15 100BASE-T4 0, RO/P Description 100BASE-T4 Capable: 0 = Device not able to perform 100BASE-T4 mode. 14 100BASE-TX 1, RO/P Full Duplex 13 100BASE-TX 1 = Device able to perform 100BASE-TX in full duplex mode. 1, RO/P Half Duplex 12 10BASE-T 10BASE-T 100BASE-TX Half Duplex Capable: 1 = Device able to perform 100BASE-TX in half duplex mode.
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7.1.3 PHY Identifier Register #1 (PHYIDR1) Table 14. PHY Identifier Register #1 (PHYIDR1), address 0x02 Bit Bit Name 15:0 OUI_MSB Default Description <0010 0000 0000 OUI Most Significant Bits: Bits 3 to 18 of the OUI (080017h) are 0000>, RO/P stored in bits 15 to 0 of this register. The most significant two bits of the OUI are ignored (the IEEE standard refers to these as bits 1 and 2). 7.1.4 PHY Identifier Register #2 (PHYIDR2) Table 15.
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DP83848J Table 16. Negotiation Advertisement Register (ANAR), address 0x04 (Continued) Bit Bit Name Default 11 ASM_DIR 0, RW Description Asymmetric PAUSE Support for Full Duplex Links: The ASM_DIR bit indicates that asymmetric PAUSE is supported. Encoding and resolution of PAUSE bits is defined in IEEE 802.3 Annex 28B, Tables 28B-2 and 28B-3, respectively. Pause resolution status is reported in PHYCR[13:12].
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This register contains the advertised abilities of the Link Partner as received during Auto-Negotiation. The content changes after the successful auto-negotiation if Next-pages are supported. Table 17. Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page), address 0x05 Bit Bit Name Default 15 NP 0, RO Description Next Page Indication: 0 = Link Partner does not desire Next Page Transfer. 1 = Link Partner desires Next Page Transfer.
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DP83848J 7.1.7 Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page) Table 18. Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page), address 0x05 Bit Bit Name Default 15 NP 0, RO Description Next Page Indication: 1 = Link Partner desires Next Page Transfer. 0 = Link Partner does not desire Next Page Transfer. 14 ACK 0, RO Acknowledge: 1 = Link Partner acknowledges reception of the ability data word. 0 = Not acknowledged.
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Bit Bit Name Default 0 LP_AN_ABLE 0, RO Description Link Partner Auto-Negotiation Able: 1 = indicates that the Link Partner supports Auto-Negotiation. 0 = indicates that the Link Partner does not support Auto-Negotiation. 7.1.9 Auto-Negotiation Next Page Transmit Register (ANNPTR) This register contains the next page information sent by this device to its Link Partner during Auto-Negotiation. Table 20.
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DP83848J 7.2 EXTENDED REGISTERS 7.2.1 PHY Status Register (PHYSTS) This register provides a single location within the register set for quick access to commonly accessed information. Table 21. PHY Status Register (PHYSTS), address 0x10 Bit Bit Name Default Description 15 RESERVED 0, RO RESERVED: Write ignored, read as 0. 14 MDI-X mode 0, RO MDI-X mode as reported by the Auto-Negotiation logic: This bit will be affected by the settings of the MDIX_EN and FORCE_MDIX bits in the PHYCR register.
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DP83848J Table 21. PHY Status Register (PHYSTS), address 0x10 (Continued) Bit Bit Name Default 4 Auto-Neg Complete 0, RO Description Auto-Negotiation Complete: 1 = Auto-Negotiation complete. 0 = Auto-Negotiation not complete. 3 Loopback Status 0, RO Loopback: 1 = Loopback enabled. 0 = Normal operation. 2 Duplex Status 0, RO Duplex: This bit indicates duplex status and is determined from Auto-Negotiation or Forced Modes. 1 = Full duplex mode. 0 = Half duplex mode.
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DP83848J 7.2.2 False Carrier Sense Counter Register (FCSCR) This counter provides information required to implement the “False Carriers” attribute within the MAU managed object class of Clause 30 of the IEEE 802.3u specification. Table 22.
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DP83848J 7.2.4 100 Mb/s PCS Configuration and Status Register (PCSR) Table 24. 100 Mb/s PCS Configuration and Status Register (PCSR), address 0x16 Bit Bit Name Default 15:13 RESERVED <00>, RO 12 RESERVED 0 Description RESERVED: Writes ignored, Read as 0. RESERVED: Must be zero. 11 RESERVED 0 10 TQ_EN 0, RW RESERVED: Must be zero. 100Mbs True Quiet Mode Enable: 1 = Transmit True Quiet Mode. 0 = Normal Transmit Mode.
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DP83848J 7.2.5 RMII and Bypass Register (RBR) This register configures the RMII Mode of operation. When RMII mode is disabled, the RMII functionality is bypassed. Table 25. RMII and Bypass Register (RBR), addresses 0x17 Bit Bit Name Default 15:6 RESERVED 0, RO 5 RMII_MODE Strap, RW Description RESERVED: Writes ignored, Read as 0. Reduced MII Mode: 0 = Standard MII Mode 1 = Reduced MII Mode 4 RMII_REV1_0 0, RW Reduce MII Revision 1.0: 0 = (RMII revision 1.
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This register provides the ability to directly control the LED outputs. It does not provide read access to the LEDs. Table 26. LED Direct Control Register (LEDCR), address 0x18 Bit Bit Name Default 15:6 RESERVED 0, RO 5 DRV_SPDLED 0, RW Description RESERVED: Writes ignored, read as 0.
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DP83848J 7.2.7 PHY Control Register (PHYCR) Table 27. PHY Control Register (PHYCR), address 0x19 Bit Bit Name Default 15 MDIX_EN Strap, RW Description Auto-MDIX Enable: 1 = Enable Auto-neg Auto-MDIX capability. 0 = Disable Auto-neg Auto-MDIX capability. The Auto-MDIX algorithm requires that the Auto-Negotiation Enable bit in the BMCR register to be set. If Auto-Negotiation is not enabled, Auto-MDIX should be disabled as well. 14 FORCE_MDIX 0, RW Force MDIX: 1 = Force MDI pairs to cross.
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DP83848J Table 27.
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DP83848J 7.2.8 10Base-T Status/Control Register (10BTSCR) Table 28. 10Base-T Status/Control Register (10BTSCR), address 0x1A Bit Bit Name Default 15 RESERVED 0, RW Description RESERVED: Must be zero. 14:12 RESERVED 0, RW RESERVED: Must be zero. 11:9 SQUELCH 100, RW Squelch Configuration: Used to set the Squelch ‘ON’ threshold for the receiver. Default Squelch ON is 330mV peak.
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DP83848J 7.2.9 CD Test and BIST Extensions Register (CDCTRL1) Table 29. CD Test and BIST Extensions Register (CDCTRL1), address 0x1B Bit Bit Name Default 15:8 BIST_ERROR_CO UNT 0, RO RESERVED 0, RW 7:6 Description BIST ERROR Counter: Counts number of errored data nibbles during Packet BIST. This value will reset when Packet BIST is restarted. The counter sticks when it reaches its max count. RESERVED: Must be zero.
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DP83848J 7.2.10 Energy Detect Control (EDCR) Table 30. Energy Detect Control (EDCR), address 0x1D Bit Bit Name Default 15 ED_EN 0, RW Description Energy Detect Enable: Allow Energy Detect Mode. When Energy Detect is enabled and Auto-Negotiation is disabled via the BMCR register, Auto-MDIX should be disabled via the PHYCR register. 14 ED_AUTO_UP 1, RW Energy Detect Automatic Power Up: Automatically begin power up sequence when Energy Detect Data Threshold value (EDCR[3:0]) is reached.
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DP83848J 8.0 Electrical Specifications Note: All parameters are guaranteed by test, statistical analysis or design. Absolute Maximum Ratings Recommended Operating Conditions Supply Voltage (VCC) Supply voltage (VCC) -0.5 V to 4.2 V 3.3 Volts + .3V DC Input Voltage (VIN) -0.5V to VCC + 0.5V Commercia - Ambient Temperature (TA) DC Output Voltage (VOUT) -0.5V to VCC + 0.5V Power Dissipation (PD) Storage Temperature (TSTG) 147.7 °C Max. die temperature (Tj) 150 °C Lead Temp.
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DP83848J Symbol Pin Types Parameter Conditions Min Typ Max Units CIN1 I CMOS Input Capacitance 5 pF COUT1 O CMOS Output Capacitance 5 pF SDTHon PMD Input Pair 100BASE-TX Signal detect turnon threshold SDTHoff PMD Input Pair 100BASE-TX Signal detect turnoff threshold VTH1 PMD Input Pair 10BASE-T Receive Threshold Idd100 Supply Idd10 Supply 1000 200 mV diff pk-pk 585 100BASE-TX (Full Duplex) IOUT = 0 mA 10BASE-T (Full Duplex) IOUT = 0 mA See mV 81 mA 92 mA Note1
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DP83848J 8.2 AC SPECS 8.2.1 Power Up Timing Vcc X1 clock T2.1.1 Hardware RESET_N 32 clocks MDC T2.1.2 Latch-In of Hardware Configuration Pins T2.1.3 input Dual Function Pins Become Enabled As Outputs Parameter Description output Notes Min Typ Max Units T2.1.1 Post Power Up Stabilization MDIO is pulled high for 32-bit serial mantime prior to MDC preamble for agement initialization register accesses X1 Clock must be stable for a min. of 167ms at power up. 167 ms T2.1.
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DP83848J 8.2.2 Reset Timing Vcc X1 clock T2.2.4 T2.2.1 Hardware RESET_N 32 clocks MDC T2.2.2 Latch-In of Hardware Configuration Pins T2.2.3 input output Dual Function Pins Become Enabled As Outputs Parameter Description Notes Min Typ Max Units T2.2.1 Post RESET Stabilization time MDIO is pulled high for 32-bit serial manprior to MDC preamble for reg- agement initialization ister accesses 3 µs T2.2.
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DP83848J 8.2.3 MII Serial Management Timing MDC T2.3.4 T2.3.1 MDIO (output) MDC T2.3.2 Valid Data MDIO (input) Parameter T2.3.3 Description Notes Min T2.3.1 MDC to MDIO (Output) Delay Time 0 T2.3.2 MDIO (Input) to MDC Setup Time 10 T2.3.3 MDIO (Input) to MDC Hold Time 10 T2.3.4 MDC Frequency Typ Max Units 30 ns ns ns 2.5 25 MHz 8.2.4 100 Mb/s MII Transmit Timing T2.4.1 T2.4.1 TX_CLK T2.4.2 TXD[3:0] TX_EN Parameter T2.4.
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DP83848J 8.2.5 100 Mb/s MII Receive Timing T2.5.1 T2.5.1 RX_CLK T2.5.2 RXD[3:0] RX_DV RX_ER Valid Data Parameter Description Notes Min Typ Max Units 20 24 ns 30 ns T2.5.1 RX_CLK High/Low Time 100 Mb/s Normal mode 16 T2.5.2 RX_CLK to RXD[3:0], RX_DV, RX_ER Delay 100 Mb/s Normal mode 10 Note: RX_CLK may be held low or high for a longer period of time during transition between reference and recovered clocks. Minimum high and low times will not be violated. 8.2.
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DP83848J 8.2.7 100BASE-TX Transmit Packet Deassertion Timing TX_CLK TX_EN TXD T2.7.1 PMD Output Pair Parameter T2.7.1 DATA DATA (T/R) (T/R) Description TX_CLK to PMD Output Pair Deassertion Notes 100 Mb/s Normal mode IDLE IDLE Min Typ 6 Max Units bits Note: Deassertion is determined by measuring the time from the first rising edge of TX_CLK occurring after the deassertion of TX_EN to the first bit of the “T” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100 Mb/s mode.
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DP83848J 8.2.8 100BASE-TX Transmit Timing (tR/F & Jitter) T2.8.1 +1 rise 90% 10% PMD Output Pair 10% +1 fall 90% T2.8.1 -1 fall -1 rise T2.8.1 T2.8.1 T2.8.2 PMD Output Pair eye pattern Parameter T2.8.1 T2.8.2 T2.8.2 Description Notes Min Typ Max Units 3 4 5 ns 100 Mb/s tR and tF Mismatch 500 ps 100 Mb/s PMD Output Pair Transmit Jitter 1.
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DP83848J 8.2.9 100BASE-TX Receive Packet Latency Timing PMD Input Pair IDLE Data (J/K) T2.9.1 CRS T2.9.2 RXD[3:0] RX_DV RX_ER Parameter Description Notes Min Typ Max Units T2.9.1 Carrier Sense ON Delay 100 Mb/s Normal mode 20 bits T2.9.2 Receive Data Latency 100 Mb/s Normal mode 24 bits Note: Carrier Sense On Delay is determined by measuring the time from the first bit of the “J” code group to the assertion of Carrier Sense.
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DP83848J 8.2.11 10 Mb/s MII Transmit Timing T2.11.1 T2.11.1 TX_CLK T2.11.2 TXD[3:0] TX_EN Parameter T2.11.3 Valid Data Description Notes Min Typ Max Units 200 210 T2.11.1 TX_CLK High/Low Time 10 Mb/s MII mode 190 ns T2.11.2 TXD[3:0], TX_EN Data Setup to TX_CLK fall 10 Mb/s MII mode 25 ns T2.11.3 TXD[3:0], TX_EN Data Hold from TX_CLK rise 10 Mb/s MII mode 0 ns Note: An attached Mac should drive the transmit signals using the positive edge of TX_CLK.
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DP83848J 8.2.13 10BASE-T Transmit Timing (Start of Packet) TX_CLK TX_EN TXD PMD Output Pair T2.13.1 Parameter T2.13.1 Description Notes Transmit Output Delay from the Min 10 Mb/s MII mode Typ Max 3.5 Units bits Falling Edge of TX_CLK Note: 1 bit time = 100 ns in 10Mb/s. 8.2.14 10BASE-T Transmit Timing (End of Packet) TX_CLK TX_EN 0 PMD Output Pair T2.14.1 0 T2.14.2 PMD Output Pair Parameter T2.14.
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DP83848J 8.2.15 10BASE-T Receive Timing (Start of Packet) 1st SFD bit decoded 1 0 1 0 1 0 1 0 1 0 1 1 TPRD± T2.15.1 CRS RX_CLK T2.15.2 RX_DV T2.15.3 0000 RXD[3:0] Parameter Preamble Description SFD Notes Min Data Typ Max Units 1000 ns T2.15.1 Carrier Sense Turn On Delay (PMD Input Pair to CRS) 630 T2.15.2 RX_DV Latency 10 bits T2.15.
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DP83848J 8.2.17 10 Mb/s Heartbeat Timing TX_EN TX_CLK T2.17.1 T2.17.2 COL Parameter Description Notes Min Typ Max Units T2.17.1 CD Heartbeat Delay All 10 Mb/s modes 1200 ns T2.17.2 CD Heartbeat Duration All 10 Mb/s modes 1000 ns 8.2.18 10 Mb/s Jabber Timing TXE T2.18.1 T2.18.2 PMD Output Pair COL Parameter Description Notes Min Typ Max Units T2.18.1 Jabber Activation Time 85 ms T2.18.2 Jabber Deactivation Time 500 ms 71 www.national.
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DP83848J 8.2.19 10BASE-T Normal Link Pulse Timing T2.19.2 T2.19.1 Normal Link Pulse(s) Parameter Description Notes Min Typ Max Units T2.19.1 Pulse Width 100 ns T2.19.2 Pulse Period 16 ms Note: These specifications represent transmit timings. 8.2.20 Auto-Negotiation Fast Link Pulse (FLP) Timing T2.20.2 T2.20.3 T2.20.1 T2.20.1 Fast Link Pulse(s) clock pulse data pulse clock pulse T2.20.5 T2.20.4 FLP Burst Parameter FLP Burst Description Notes Min Typ Max Units T2.20.
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DP83848J 8.2.21 100BASE-TX Signal Detect Timing PMD Input Pair T2.21.1 T2.21.2 SD+ internal Parameter Description Notes Min Typ Max Units T2.21.1 SD Internal Turn-on Time 1 ms T2.21.2 SD Internal Turn-off Time 350 µs Max Units 240 ns Note: The signal amplitude on PMD Input Pair must be TP-PMD compliant. 8.2.22 100 Mb/s Internal Loopback Timing TX_CLK TX_EN TXD[3:0] CRS T2.22.1 RX_CLK RX_DV RXD[3:0] Parameter T2.22.
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DP83848J 8.2.23 10 Mb/s Internal Loopback Timing TX_CLK TX_EN TXD[3:0] CRS T2.23.1 RX_CLK RX_DV RXD[3:0] Parameter T2.23.1 Description TX_EN to RX_DV Loopback Notes Min 10 Mb/s internal loopback mode Note: Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN. www.national.
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DP83848J 8.2.24 RMII Transmit Timing T2.24.1 X1 T2.24.2 TXD[1:0] TX_EN T2.24.3 Valid Data T2.24.4 PMD Output Pair Parameter Symbol Description Notes Min 50 MHz Reference Clock Typ T2.24.1 X1 Clock Period T2.24.2 TXD[1:0], TX_EN, Data Setup to X1 rising 4 ns T2.24.3 TXD[1:0], TX_EN, Data Hold from X1 rising 2 ns T2.24.4 X1 Clock to PMD Output Pair From X1 Rising edge to first bit of symbol Latency 75 20 Max Units 17 ns bits www.national.
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DP83848J 8.2.25 RMII Receive Timing PMD Input Pair IDLE Data (J/K) Data (TR) T2.25.4 T2.25.5 X1 T2.25.2 T2.25.1 T2.25.2 T2.25.3 T2.25.2 RX_DV CRS_DV T2.25.2 RXD[1:0] RX_ER Parameter Description Notes Min 50 MHz Reference Clock Typ Max 20 Units T2.25.1 X1 Clock Period T2.25.2 RXD[1:0], CRS_DV, RX_DV, and RX_ER output delay from X1 rising T2.25.3 CRS ON delay From JK symbol on PMD Receive Pair to initial assertion of CRS_DV 18.5 bits T2.25.
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DP83848J 8.2.26 Isolation Timing Clear bit 10 of BMCR (return to normal operation from Isolate mode) T2.26.1 H/W or S/W Reset (with PHYAD = 00000) T2.26.2 MODE ISOLATE Parameter Description Notes NORMAL Max Units T2.26.1 From software clear of bit 10 in the BMCR register to the transition from Isolate to Normal Mode Min Typ 100 µs T2.26.2 From Deassertion of S/W or H/W Reset to transition from Isolate to Normal mode 500 µs Max Units 5 ns 8.2.27 100 Mb/s X1 to TX_CLK Timing X1 T2.27.
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DP83848J PHYTERR Mini LS - Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver Physical Dimensions inches (millimeters) unless otherwise noted THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PROCUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE.
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