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DP83849I

DP83849I PHYTER DUAL Industrial Temperature with Flexible Port Switching

Dual Port 10/100 Mb/s Ethernet Physical Layer Transceiver

Literature Number: SNOSAX1D

Summary of content (108 pages)

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DP83849I DP83849I PHYTER DUAL Industrial Temperature with Flexible Port Switching Dual Port 10/100 Mb/s Ethernet Physical Layer Transceiver Literature Number: SNOSAX1D
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DP83849I PHYTER® DUAL Industrial Temperature with Flexible Port Switching Dual Port 10/100 Mb/s Ethernet Physical Layer Transceiver General Description Features The number of applications requiring Ethernet Connectivity continues to expand. Along with this increased market demand is a change in application requirements.
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DP83849I MII MANAGEMENT INTERFACE PORT A MII/RMII/SNI TX RX MDC PORT B MII/RMII/SNI TX MDIO RX MANAGEMENT INTERFACE 10/100 PHY CORE 10/100 PHY CORE PORT A PORT B BOUNDARY SCAN LED DRIVERS LEDS TPTD± TPRD± JTAG LED DRIVERS LEDS TPTD± TPRD± Figure 1. DP83849I Functional Block Diagram www.national.
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1.0 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.1 Serial Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 1.2 MAC Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 1.3 Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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DP83849I 4.2.1 Analog Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2 Digital Signal Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2.1 Digital Adaptive Equalization and Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2.2 Base Line Wander Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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59 60 61 62 63 65 65 66 7.2 Extended Registers - Page 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 7.2.1 False Carrier Sense Counter Register (FCSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.2 Receiver Error Counter Register (RECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.3 100 Mb/s PCS Configuration and Status Register (PCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.
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DP83849I 8.2.29 8.2.30 8.2.31 8.2.32 Single Clock MII (SCMII) Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Isolation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLK2MAC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Mb/s X1 to TX_CLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Figure 1. DP83849I Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Figure 2. PHYAD Strapping Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 3. AN Strapping and LED Loading Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 4. MII Port Mapping . . . . . . . . . . . . . . . . . . . . . .
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DP83849I List of Table Table 1. Auto-Negotiation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Table 2. PHY Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Table 3. LED Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Table 4.
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11 12 13 14 15 16 17 18 19 20 TX_CLK_A TX_EN_A TXD0_A TXD1_A TXD2_A TXD3_A/SNI_MODE_A PWRDOWN_INT_A LED_LINK_A/AN0_A LED_SPEED_A/AN1_A 10 IOVDD1 IOGND1 9 6 COREGND1 RXD3_A/ED_EN_A 5 RXD1_A/PHYAD2 8 4 RXD0_A/PHYAD1 7 3 COL_A RXD2_A/CLK2MAC_DIS 2 PFBIN1 1 RX_ER_A/MDIX_EN_A o CRS_A/CRS_DV_A/LED_CFG_A RX_ER_B/MDIX_EN_B COL_B RXD0_B/PHYAD3 RXD1_B/PHYAD4 RXD2_B/EXTENDER_EN COREGND2 PFBIN4 RXD3_B/ED_EN_B IOGND2 IOVDD2 TX_CLK_B TX_EN_B TXD0_B TXD1_B TXD2_B TXD3_B/SNI_MODE_B PWRDOWN_INT_B LED
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DP83849I 1.0 Pin Descriptions The DP83849I pins are classified into the following interface categories (each interface is described in the sections that follow): Note: Strapping pin option. Please see Section 1.7 for strap definitions.
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RX_CLK_A Type Pin # Description O 79 MII RECEIVE CLOCK: Provides the 25 MHz recovered receive clocks for 100 Mb/s mode and 2.5 MHz for 10 Mb/s mode. RX_CLK_B 63 Unused in RMII mode. The device uses the X1 reference clock input as the 50 MHz reference for both transmit and receive. SNI RECEIVE CLOCK: Provides the 10 MHz recovered receive clocks for 10 Mb/s SNI mode.
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DP83849I 1.3 Clock Interface Signal Name X1 Type Pin # Description I 70 CRYSTAL/OSCILLATOR INPUT: This pin is the primary clock reference input for the DP83849I and must be connected to a 25 MHz 0.005% (+50 ppm) clock source. The DP83849I supports either an external crystal resonator connected across pins X1 and X2, or an external CMOS-level oscillator source connected to pin X1 only.
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DP83849I 1.5 JTAG Interface Signal Name TCK Type Pin # I, PU 72 Description TEST CLOCK This pin has a weak internal pullup. TDO O 73 TEST OUTPUT TMS I, PU 74 TEST MODE SELECT TRSTN I, PU 75 This pin has a weak internal pullup. TEST RESET Active low test reset. This pin has a weak internal pullup. TDI I, PU 76 TEST DATA INPUT This pin has a weak internal pullup. 1.
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DP83849I Signal Name AN_EN (LED_ACT/LED_COL_A) Type Pin # Description S, O, PU 21 Auto-Negotiation Enable: When high, this enables Auto-Negotiation with the capability set by AN0 and AN1 pins. When low, this puts the part into Forced Mode with the capability set by AN0 and AN1 pins.
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Type Pin # Description 2 MDIX ENABLE: Default is to enable MDIX. This strapping option disables Auto-MDIX. An external pull-down will disable AutoMDIX mode. MDIX_EN_A (RX_ER_A) MDIX_EN_B (RX_ER_B) S, O, PU ED_EN_A (RXD3_A) ED_EN_B (RXD3_B) S, O, PD CLK2MAC_DIS (RXD2_A) S, O, PD 8 Clock to MAC Disable: This strapping option disables (floats) the CLK2MAC pin. Default is to enable CLK2MAC output. An external pullup will disable (float) the CLK2MAC pin.
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DP83849I 1.8 10 Mb/s and 100 Mb/s PMD Interface Signal Name Type Pin # I/O 26 10BASE-T or 100BASE-TX Transmit Data TPTDP_A 27 TPTDM_B 36 TPTDP_B 35 In 10BASE-T or 100BASE-TX: Differential common driver transmit output (PMD Output Pair). These differential outputs are automatically configured to either 10BASE-T or 100BASE-TX signaling. TPTDM_A Description In Auto-MDIX mode of operation, this pair can be used as the Receive Input pair. These pins require 3.3V bias for operation.
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VHB80A Pin Pin Name # VHB80A Pin Pin Name # 1 CRS_A/CRS_DV_A/LED_CFG_A 2 RX_ER_A/MDIX_EN_A 3 COL_A 4 RXD0_A/PHYAD1 5 RXD1_A/PHYAD2 6 COREGND1 7 PFBIN1 8 RXD2_A/CLK2MAC_DIS 9 RXD3_A/ED_EN_A 10 IOGND1 11 IOVDD1 12 TX_CLK_A 13 TX_EN_A 14 TXD0_A 15 TXD1_A 16 TXD2_A 17 TXD3_A/SNI_MODE_A 18 PWRDOWN_INT_A 19 LED_LINK_A/AN0_A 20 LED_SPEED_A/AN1_A 21 LED_ACT/LED_COL/AN_EN_A 22 ANAGND1 23 TPRDM_A 24 TPRDP_A 25 CDGND1 26 TPTDM_A 27 TPTDP_A 28 PFBIN2 29 ANAGND2
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DP83849I 2.0 Configuration This section includes information on the various configuration options available with the DP83849I. The configuration options described below include: — — — — — — — Table 1. Auto-Negotiation Modes Media Configuration Auto-Negotiation PHY Address and LEDs Half Duplex vs. Full Duplex Isolate mode Loopback mode BIST 2.
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The Auto-Negotiation Link Partner Ability Register (ANLPAR) at address 05h is used to receive the base link code word as well as all next page code words during the negotiation. Furthermore, the ANLPAR will be updated to either 0081h or 0021h for parallel detection to either 100 Mb/s or 10 Mb/s respectively. 2.1.
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The DP83849I supports PHY Address strapping of Port A to even values 0 (<0000_0>) through 30 (<1111_0>). Port B is strapped to odd values 1 (<0000_1>) through 31 (<1111_1>). Note that Port B address is always 1 greater than Port A address. For further detail relating to the latch-in timing requirements of the PHY Address pins, as well as the other hardware configuration pins, refer to the Reset summary in Section 6.0. 2.3.
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The DP83849I supports three configurable Light Emitting Diode (LED) pins for each port. Several functions can be multiplexed onto the three LEDs using three different modes of operation. The LED operation mode can be selected by writing to the LED_CFG[1:0] register bits in the PHY Control Register (PHYCR) at address 19h, bits [6:5]. In addition, LED_CFG[0] for each port can be set by a strap option on the CRS_A and CRS_B pins.
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AN_EN_A =0 It is important to understand that while Auto-Negotiation with the use of Fast Link Pulse code words can interpret and configure to full-duplex operation, parallel detection can not recognize the difference between full and halfduplex from a fixed 10 Mb/s or 100 Mb/s link partner over twisted pair. As specified in the 802.
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The DP83849I supports several modes of operation using the MII interface pins. The options are defined in the following sections and include: — MII Mode — RMII Mode — 10 Mb Serial Network Interface (SNI) — Single Clock MII Mode (SCMII) In addition, the DP83849I supports the standard 802.3u MII Serial Management Interface and a Flexible MII Port Assignment scheme. The modes of operation can be selected by strap options or register control.
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DP83849I 3.2 Reduced MII Interface The DP83849I incorporates the Reduced Media Independent Interface (RMII) as specified in the RMII specification (rev1.2) from the RMII Consortium. This interface may be used to connect PHY devices to a MAC in 10/100 Mb/s systems using a reduced number of pins. In this mode, data is transferred 2-bits at a time using the 50 MHz RMII_REF clock for both transmit and receive.
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3.4 Single Clock MII Mode The DP83849I incorporates a 10 Mb Serial Network Interface (SNI) which allows a simple serial data interface for 10 Mb only devices. This is also referred to as a 7-wire interface. While there is no defined standard for this interface, it is based on early 10 Mb physical layer devices. Data is clocked serially at 10 MHz using separate transmit and receive paths.
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DP83849I 3.5 Flexible MII Port Assignment The DP83849I supports a flexible assignment scheme for each of the channels to the MII/RMII interface. Either of the MII ports may be assigned to the internal channels A/B. These values are controlled by the RMII and Bypass Register (RBR), address 17h. Transmit assignments and Receive assignments can be made separately to allow even more flexibility (i.e. both channels could transmit from MII A while still allowing separate receive paths for the channels).
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Note that Channel A is the master of MII Port A, and Chan- RX MII Port Mapping controls and configurations are nel B is the master of MII Port B. This means that in order shown in the following tables: for Channel B to control MII Port A, Channel A must be configured to either control MII Port B or be Disabled; the reverse is also true. Table 6. RX MII Port Mapping Controls RBR[12:11] Desired RX Channel Destination 00 Normal Port 01 Opposite Port 10 Both Ports 11 Disabled Table 7.
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DP83849I 3.5.2 TX MII Port Mapping TX MII Port Mapping controls and configurations are shown in the following tables: Table 8. TX MII Port Mapping Controls RBR[10:9] TX Channel Source 00 Normal Port 01 Opposite Port 10 Opposite RX Port 11 Disabled Table 9. TX MII Port Mapping Configurations Channel A RBR[10:9] Port A TX Source Channel B RBR[10:9] Port B TX Source 00 MII Port A 00 MII Port B 01 MII Port B 01 MII Port A 10 RX Channel B 10 RX Channel A 11 Disabled 11 Disabled 3.
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The DP83849I provides a simple strap option to automatically configure both channels for Extender Mode with no device register configuration necessary. The EXTENDER_EN Strap can be used in conjunction with the Auto-Negotiation Straps (AN_EN, AN0, AN1), the RMII Mode Strap to allow many possible configurations. If Extender Mode is strapped but RMII Mode is not, both channels will automatically be configured for Single Clock MII Receive and Transmit Modes.
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DP83849I 3.6 802.3u MII Serial Management Interface The DP83849I waits until it has received this preamble sequence before responding to any other transaction. Once the DP83849I serial management port has been initialized no further preamble sequencing is required until after a power-on/reset, invalid Start, invalid Opcode, or invalid turnaround bit has occurred. 3.6.
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DP83849I MDC MDIO Z Z (STA) Z Idle 0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Start Opcode (Write) PHY Address (PHYAD = 0Ch) Register Address (00h = BMCR) TA Register Data Z Idle Figure 6. Typical MDC/MDIO Write Operation 3.6.3 Serial Management Preamble Suppression The DP83849I supports a Preamble Suppression mode as indicated by a one in bit 6 of the Basic Mode Status Register (BMSR, address 01h.) If the station management entity (i.e.
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DP83849I 4.0 Architecture This section describes the operations within each transceiver module, 100BASE-TX and 10BASE-T. Each operation consists of several functional blocks and described in the following: The block diagram in Figure 7. provides an overview of each functional block within the 100BASE-TX transmit section.
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DP83849I Table 13.
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DP83849I 4.1.1 Code-group Encoding and Injection The code-group encoder converts 4-bit (4B) nibble data generated by the MAC into 5-bit (5B) code-groups for transmission. This conversion is required to allow control data to be combined with packet data code-groups. Refer to Table 13 for 4B to 5B code-group mapping details. The code-group encoder substitutes the first 8-bits of the MAC preamble with a J/K code-group pair (11000 10001) upon transmission.
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DP83849I RX_DV/CRS RX_CLK RXD[3:0] / RX_ER 4B/5B DECODER SERIAL TO PARALLEL CODE GROUP ALIGNMENT RX_DATA VALID SSD DETECT LINK INTEGRITY MONITOR DESCRAMBLER NRZI TO NRZ DECODER MLT-3 TO BINARY DECODER SIGNAL DETECT DIGITAL SIGNAL PROCESSOR ANALOG FRONT END RD +/− Figure 8. 100BASE-TX Receive Block Diagram 35 www.national.
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DP83849I 4.2.2.1 Digital Adaptive Equalization and Gain Control When transmitting data at high speeds over copper twisted pair cable, frequency dependent attenuation becomes a concern. In high-speed twisted pair signalling, the frequency content of the transmitted signal can vary greatly during normal operation based primarily on the randomness of the scrambled data stream. This variation in signal attenuation caused by frequency variations must be compensated to ensure the integrity of the transmission.
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DP83849I 4.2.2.2 Base Line Wander Compensation Figure 10. 100BASE-TX BLW Event The DP83849I is completely ANSI TP-PMD compliant and includes Base Line Wander (BLW) compensation. The BLW compensation block can successfully recover the TPPMD defined “killer” pattern. PMD Standard as well as the IEEE 802.3 100BASE-TX Standard for both voltage thresholds and timing parameters.
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DP83849I 4.2.7 Descrambler Signal detect must be valid for 395us to allow the link monitor to enter the 'Link Up' state, and enable the transmit and receive functions. A serial descrambler is used to de-scramble the received NRZ data. The descrambler has to generate an identical data scrambling sequence (N) in order to recover the original unscrambled data (UD) from the scrambled data (SD) 4.2.
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the circuitry that valid data is present. At this time, the smart squelch circuitry is reset. Valid data is considered to be present until the squelch level has not been generated for a time longer than 150 ns, indicating the End of Packet. Once good data has been detected, the squelch levels are reduced to minimize the effect of noise causing premature End of Packet detection.
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DP83849I 4.3.3 Collision Detection and SQE When in Half Duplex, a 10BASE-T collision is detected when the receive and transmit channels are active simultaneously. Collisions are reported by the COL signal on the MII. Collisions are also reported when a jabber condition is detected. The COL signal remains set for the duration of the collision. If the PHY is receiving when a collision is detected it is reported immediately (through the COL pin).
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5.1 TPI Network Circuit Figure 12 shows the recommended circuit for a 10/100 Mb/s twisted pair interface. Below is a partial list of recommended transformers. It is important that the user realize that variations with PCB and component characteristics requires that the application be tested to ensure that the circuit meets the requirements of the intended application. Pulse H1102 Pulse H2019 Belfuse S558-5999-U7 Halo TG110-S050N2RL Vdd TPRDM Vdd COMMON MODE CHOKES MAY BE REQUIRED. 49.9Ω 0.
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DP83849I 5.2 ESD Protection Typically, ESD precautions are predominantly in effect when handling the devices or board before being installed in a system. In those cases, strict handling procedures need be implemented during the manufacturing process to greatly reduce the occurrences of catastrophic ESD events. After the system is assembled, internal components are less sensitive from ESD events. capacitor values will vary with the crystal vendors; check with the vendor for the recommended loads.
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Parameter Min Typ Frequency Max Units 50 Condition MHz Frequency +50 ppm Operational Temperature +50 ppm Operational Temperature Rise / Fall Time 6 nsec 20% - 80% Jitter 8001 psec Short term Jitter 8001 psec Long term Tolerance Frequency Stability Symmetry 1 40% 60% Duty Cycle This limit is provided as a guideline for component selection and to guaranteed by production testing.
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DP83849I 5.5 Power Down/Interrupt 5.6 Energy Detect Mode The Power Down and Interrupt functions are multiplexed on pin 18 and pin 44 of the device. By default, this pin functions as a power down input and the interrupt function is disabled. Setting bit 0 (INT_OE) of MICR (11h) will configure the pin as an active low interrupt output. Ports A and B can be powered down individually, using the separate PWRDOWN_INT_A and PWRDOWN_INT_B pins.
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The DP83849I provides a method of estimating cable length based on electrical characteristics of the 100Mb Link. This essentially provides an effective cable length rather than a measurement of the physical cable length. The cable length estimation is only available in 100Mb mode of operation with a valid Link status. The cable length estimation is available at the Link Diagnostics Registers - Page 2, register 100Mb Length Detect (LEN100_DET), address 14h.
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DP83849I Table 17. Link Quality Monitor Parameter Ranges Parameter Minimum Value Maximum Value Min (2-s comp) Max (2-s comp) -128 +127 0x80 0x7F DAGC 0 +255 0x00 0xFF DBLW -128 +127 0x80 0x7F Freq Offset -128 +127 0x80 0x7F Freq Control -128 +127 0x80 0x7F DEQ C1 5.7.3 TDR Cable Diagnostics The DP83849I implements a Time Domain Reflectometry (TDR) method of cable length measurement and evaluation which can be used to evaluate a connected twisted pair cable.
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5.7.3.4 TDR Results The TDR function monitors data from the Analog to Digital Converter (ADC) to detect both peak values and values above a programmable threshold. It can be programmed to detect maximum or minimum values. In addition, it records the time, in 8ns intervals, at which the peak or threshold value first occurs.
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DP83849I 6.0 Reset Operation The DP83849I includes an internal power-on reset (POR) function and does not need to be explicitly reset for normal operation after power up. If required during normal operation, the device can be reset by a hardware or software reset. (BMCR). The period from the point in time when the reset bit is set to the point in time when software reset has concluded is approximately 1 µs.
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DP83849I 7.0 Register Block Table 18.
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www.national.com 50 11h 12h 13h 14h 15h 16h MII Interrupt Control Register MII Interrupt Status and Misc.
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DP83849I 7.
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DP83849I 7.1.1 Basic Mode Control Register (BMCR) Table 20. Basic Mode Control Register (BMCR), address 00h Bit Bit Name Default 15 RESET 0, RW/SC Description Reset: 1 = Initiate software Reset / Reset in Process. 0 = Normal operation. This bit, which is self-clearing, returns a value of one until the reset process is complete. The configuration is re-strapped. 14 LOOPBACK 0, RW Loopback: 1 = Loopback enabled. 0 = Normal operation.
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DP83849I Table 20. Basic Mode Control Register (BMCR), address 00h (Continued) Bit Bit Name Default 7 COLLISION TEST 0, RW Description Collision Test: 1 = Collision test enabled. 0 = Normal operation. When set, this bit will cause the COL signal to be asserted in response to the assertion of TX_EN within 512-bit times. The COL signal will be de-asserted within 4-bit times in response to the de-assertion of TX_EN. 6:0 RESERVED 0, RO RESERVED: Write ignored, read as 0. 55 www.national.
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DP83849I 7.1.2 Basic Mode Status Register (BMSR) Table 21. Basic Mode Status Register (BMSR), address 01h Bit Bit Name Default 15 100BASE-T4 0, RO/P Description 100BASE-T4 Capable: 0 = Device not able to perform 100BASE-T4 mode. 14 100BASE-TX 1, RO/P FULL DUPLEX 13 100BASE-TX 1 = Device able to perform 100BASE-TX in full duplex mode. 1, RO/P HALF DUPLEX 12 10BASE-T 10BASE-T 100BASE-TX Half Duplex Capable: 1 = Device able to perform 100BASE-TX in half duplex mode.
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7.1.3 PHY Identifier Register #1 (PHYIDR1) Table 22. PHY Identifier Register #1 (PHYIDR1), address 02h Bit Bit Name 15:0 OUI_MSB Default Description <0010 0000 0000 OUI Most Significant Bits: Bits 3 to 18 of the OUI (080017h) are 0000>, RO/P stored in bits 15 to 0 of this register. The most significant two bits of the OUI are ignored (the IEEE standard refers to these as bits 1 and 2). 7.1.4 PHY Identifier Register #2 (PHYIDR2) Table 23.
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DP83849I Table 24. Negotiation Advertisement Register (ANAR), address 04h (Continued) Bit Bit Name Default 11 ASM_DIR 0, RW Description Asymmetric PAUSE Support for Full Duplex Links: The ASM_DIR bit indicates that asymmetric PAUSE is supported. Encoding and resolution of PAUSE bits is defined in IEEE 802.3 Annex 28B, Tables 28B-2 and 28B-3, respectively. Pause resolution status is reported in PHYCR[13:12].
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This register contains the advertised abilities of the Link Partner as received during Auto-Negotiation. The content changes after the successful auto-negotiation if Next-pages are supported. Table 25. Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page), address 05h Bit Bit Name Default 15 NP 0, RO Description Next Page Indication: 0 = Link Partner does not desire Next Page Transfer. 1 = Link Partner desires Next Page Transfer.
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DP83849I 7.1.7 Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page) Table 26. Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page), address 05h Bit Bit Name Default 15 NP 0, RO Description Next Page Indication: 1 = Link Partner desires Next Page Transfer. 0 = Link Partner does not desire Next Page Transfer. 14 ACK 0, RO Acknowledge: 1 = Link Partner acknowledges reception of the ability data word. 0 = Not acknowledged.
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DP83849I 7.1.8 Auto-Negotiate Expansion Register (ANER) This register contains additional Local Device and Link Partner status information. Table 27. Auto-Negotiate Expansion Register (ANER), address 06h Bit Bit Name Default Description 15:5 RESERVED 0, RO RESERVED: Writes ignored, Read as 0. 4 PDF 0, RO Parallel Detection Fault: 1 = A fault has been detected via the Parallel Detection function. 0 = A fault has not been detected.
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DP83849I 7.1.9 Auto-Negotiation Next Page Transmit Register (ANNPTR) This register contains the next page information sent by this device to its Link Partner during Auto-Negotiation. Table 28. Auto-Negotiation Next Page Transmit Register (ANNPTR), address 07h Bit Bit Name Default 15 NP 0, RW Description Next Page Indication: 0 = No other Next Page Transfer desired. 1 = Another Next Page desired. 14 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
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This register provides a single location within the register set for quick access to commonly accessed information. Table 29. PHY Status Register (PHYSTS), address 10h Bit Bit Name Default Description 15 RESERVED 0, RO RESERVED: Write ignored, read as 0. 14 MDIX MODE 0, RO MDIX mode as reported by the Auto-Negotiation logic: This bit will be affected by the settings of the MDIX_EN and FORCE_MDIX bits in the PHYCR register.
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DP83849I Table 29. PHY Status Register (PHYSTS), address 10h Bit Bit Name Default 6 REMOTE FAULT 0, RO Description Remote Fault: 1 = Remote Fault condition detected (cleared on read of BMSR (address 01h) register or by reset). Fault criteria: notification from Link Partner of Remote Fault via Auto-Negotiation. 0 = No remote fault condition detected.
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This register implements the MII Interrupt PHY Specific Control register. Sources for interrupt generation include: Energy Detect State Change, Link State Change, Speed Status Change, Duplex Status Change, Auto-Negotiation Complete or any of the counters becoming half-full. The individual interrupt events must be enabled by setting bits in the MII Interrupt Status and Event Control Register (MISR). Table 30.
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DP83849I Table 31. MII Interrupt Status and Misc. Control Register (MISR), address 12h 11 DUP_INT 0, RO/COR Change of duplex status interrupt: 1 = Duplex status change interrupt is pending and is cleared by the current read. 0 = No duplex status change interrupt pending. 10 ANC_INT 0, RO/COR Auto-Negotiation Complete interrupt: 1 = Auto-negotiation complete interrupt is pending and is cleared by the current read. 0 = No Auto-negotiation complete interrupt pending.
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7.2.1 False Carrier Sense Counter Register (FCSCR) This counter provides information required to implement the “False Carriers” attribute within the MAU managed object class of Clause 30 of the IEEE 802.3u specification. Table 33. False Carrier Sense Counter Register (FCSCR), address 14h Bit Bit Name Default 15:8 RESERVED 0, RO 7:0 FCSCNT[7:0] 0, RO/COR Description RESERVED: Writes ignored, Read as 0 False Carrier Event Counter: This 8-bit counter increments on every false carrier event.
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DP83849I Table 35. 100 Mb/s PCS Configuration and Status Register (PCSR), address 16h (Continued) Bit Bit Name Default 8 SD_OPTION 1, RW Description Signal Detect Option: 1 = Default operation. Link will be asserted following detection of valid signal level and Descrambler Lock. Link will be maintained as long as signal level is valid. A loss of Descrambler Lock will not cause Link Status to drop. 0 = Modified signal detect algorithm.
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This register configures the RMII/MII Interface Mode of operation. This register controls selecting MII, RMII, or Single Clock MII mode for Receive or Transmit. In addition, several additional bits are included to allow datapath selection for Transmit and Receive in multiport applications. Table 36.
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DP83849I Table 36. RMII and Bypass Register (RBR), addresses 17h (Continued) Bit Bit Name Default 5 RMII_MODE Strap, RW Description Reduced MII Mode: 0 = Standard MII Mode 1 = Reduced MII Mode 4 RMII_REV1_0 0, RW Reduced MII Revision 1.0: 0 = (RMII revision 1.2) CRS_DV will toggle at the end of a packet to indicate deassertion of CRS. 1 = (RMII revision 1.0) CRS_DV will remain asserted until final data is transferred. CRS_DV will not toggle at the end of a packet.
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This register provides the ability to directly control any or all LED outputs. It does not provide read access to LEDs. In addition, it provides control for the Activity source and blinking LED frequency. Table 37. LED Direct Control Register (LEDCR), address 18h Bit Bit Name Default Description 15:9 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
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DP83849I 7.2.6 PHY Control Register (PHYCR) This register provides control for Phy functions such as MDIX, BIST, LED configuration, and Phy address. It also provides Pause Negotiation status. Table 38. PHY Control Register (PHYCR), address 19h Bit Bit Name Default 15 MDIX_EN Strap, RW Description Auto-MDIX Enable: 1 = Enable Auto-neg Auto-MDIX capability. 0 = Disable Auto-neg Auto-MDIX capability. The Auto-MDIX algorithm requires that the Auto-Negotiation Enable bit in the BMCR register to be set.
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DP83849I Table 38.
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DP83849I Table 39. 10Base-T Status/Control Register (10BTSCR), address 1Ah (Continued) Bit Bit Name Default 8 LOOPBACK_10_DIS 0, RW Description 10Base-T Loopback Disable: In half-duplex mode, default 10BASE-T operation loops Transmit data to the Receive data in addition to transmitting the data on the physical medium. This is for consistency with earlier 10BASE2 and 10BASE5 implementations which used a shared medium. Setting this bit disables the loopback function.
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This register controls test modes for the 10BASE-T Common Driver. In addition it contains extended control and status for the packet BIST function. Table 40. CD Test and BIST Extensions Register (CDCTRL1), address 1Bh Bit Bit Name Default 15:8 BIST_ERROR_COUNT 0, RO Description BIST ERROR Counter: Counts number of errored data nibbles during Packet BIST. This value will reset when Packet BIST is restarted. The counter sticks when it reaches its max count. 7:6 RESERVED 0, RW RESERVED: Must be zero.
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DP83849I 7.2.10 Energy Detect Control (EDCR) This register provides control and status for the Energy Detect function. Table 42. Energy Detect Control (EDCR), address 1Dh Bit Bit Name Default 15 ED_EN Strap, RW Description Energy Detect Enable: Allow Energy Detect Mode. When Energy Detect is enabled and Auto-Negotiation is disabled via the BMCR register, Auto-MDIX should be disabled via the PHYCR register.
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DP83849I 7.3 Link Diagnostics Registers - Page 2 Page 2 Link Diagnostics Registers are accessible by setting bits [1:0] = 10 of PAGESEL (13h). 7.3.1 100Mb Length Detect Register (LEN100_DET), Page 2, address 14h This register contains linked cable length estimation in 100Mb operation. The cable length is an estimation of the effective cable length based on the characteristics of the recovered signal. The cable length is valid only during 100Mb operation with a valid Link status indication. Table 43.
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DP83849I 7.3.3 TDR Control Register (TDR_CTRL), Page 2, address 16h This register contains control for the Time Domain Reflectometry (TDR) cable diagnostics. The TDR cable diagnostics sends pulses down the cable and captures reflection data to be used to estimate cable length and detect certain cabling faults. Table 45. TDR Control Register (TDR_CTRL), address 16h Bit Bit Name Default 15 TDR_ENABLE 0, RW Description TDR Enable: Enable TDR mode.
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This register contains sample window control for the Time Domain Reflectometry (TDR) cable diagnostics. The two values contained in this register specify the beginning and end times for the window to monitor the response to the transmitted pulse. Time values are in 8ns increments. This provides a method to search for multiple responses and also to screen out the initial outgoing pulse. Table 46.
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DP83849I 7.3.7 Variance Control Register (VAR_CTRL), Page 2, address 1Ah The Variance Control and Data Registers provide control and status for the Cable Signal Quality Estimation function. The Cable Signal Quality Estimation allows a simple method of determining an approximate Signal-to-Noise Ratio for the 100Mb receiver. This register contains the programmable controls and status bits for the variance computation, which can be used to make a simple Signal-to-Noise Ratio estimation. Table 49.
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This register contains the controls for the Link Quality Monitor function. The Link Quality Monitor provides a mechanism for programming a set of thresholds for DSP parameters. If the thresholds are violated, an interrupt will be asserted if enabled in the MISR. Monitor control and status are available in this register, while the LQDR register controls read/write access to threshold values and current parameter values. Reading of LQMR register clears warning bits and re-arms the interrupt generation.
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DP83849I 7.3.10 Link Quality Data Register (LQDR), Page 2 This register provides read/write control of thresholds for the 100Mb Link Quality Monitor function. The register also provides a mechanism for reading current adapted parameter values. Threshold values may not be written if the device is powered-down. Table 52. Link Quality Data Register (LQDR), address 1Eh Bit Bit Name Default Description 15:14 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
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DP83849I 8.0 Electrical Specifications Note: All parameters are guaranteed by test, statistical analysis or design. Recommended Operating Conditions Absolute Maximum Ratings Supply Voltage (VCC) Supply voltage (VCC) -0.5 V to 4.2 V 3.3 Volts + .3V DC Input Voltage (VIN) -0.5V to VCC + 0.5V Industrial - Ambient Temperature (TA) DC Output Voltage (VOUT) -0.5V to VCC + 0.5V Power Dissipation (PD) Storage Temperature (TSTG) 260 °C ESD Rating (RZAP = 1.5k, CZAP = 100 pF) 4.
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DP83849I Symbol Pin Types Parameter SDTHon PMD Input Pair 100BASE-TX Signal detect turnon threshold SDTHoff PMD Input Pair 100BASE-TX Signal detect turnoff threshold VTH1 PMD Input Pair 10BASE-T Receive Threshold Idd100 Supply 100BASE-TX (Full Duplex) 180 mA Idd10 Supply 10BASE-T (Full Duplex) 180 mA Idd Supply Power Down Mode 9.5 mA www.national.
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DP83849I 8.2 AC Specs 8.2.1 Power Up Timing Vcc X1 clock T2.1.1 Hardware RESET_N 32 clocks MDC T2.1.2 Latch-In of Hardware Configuration Pins T2.1.3 input Dual Function Pins Become Enabled As Outputs Parameter Description output Notes Min Typ Max Units T2.1.1 Post Power Up Stabilization MDIO is pulled high for 32-bit serial mantime prior to MDC preamble for agement initialization register accesses X1 Clock must be stable for a min. of 167ms at power up. 167 ms T2.1.
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DP83849I 8.2.2 Reset Timing Vcc X1 clock T2.2.1 T2.2.4 Hardware RESET_N 32 clocks MDC T2.2.2 Latch-In of Hardware Configuration Pins T2.2.3 input Dual Function Pins Become Enabled As Outputs Parameter Description output Notes Min Typ Max Units T2.2.1 Post RESET Stabilization time MDIO is pulled high for 32-bit serial manprior to MDC preamble for reg- agement initialization ister accesses 3 µs T2.2.
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DP83849I 8.2.3 MII Serial Management Timing MDC T2.3.1 T2.3.4 MDIO (output) MDC T2.3.2 Valid Data MDIO (input) Parameter T2.3.3 Description Notes Min T2.3.1 MDC to MDIO (Output) Delay Time 0 T2.3.2 MDIO (Input) to MDC Setup Time 10 T2.3.3 MDIO (Input) to MDC Hold Time 10 T2.3.4 MDC Frequency Typ Max Units 30 ns ns ns 2.5 25 MHz 8.2.4 100 Mb/s MII Transmit Timing T2.4.1 T2.4.1 TX_CLK T2.4.3 T2.4.2 TXD[3:0] TX_EN Parameter Valid Data Min Typ T2.4.
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DP83849I 8.2.5 100 Mb/s MII Receive Timing T2.5.1 T2.5.1 RX_CLK T2.5.2 RXD[3:0] RX_DV RX_ER Valid Data Parameter Description Notes Min Typ Max Units 20 24 ns 30 ns T2.5.1 RX_CLK High/Low Time 100 Mb/s Normal mode 16 T2.5.2 RX_CLK to RXD[3:0], RX_DV, RX_ER Delay 100 Mb/s Normal mode 10 Note: RX_CLK may be held low or high for a longer period of time during transition between reference and recovered clocks. Minimum high and low times will not be violated. 8.2.
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DP83849I 8.2.7 100BASE-TX MII Transmit Packet Deassertion Timing TX_CLK TX_EN TXD T2.7.1 PMD Output Pair Parameter T2.7.1 DATA DATA (T/R) (T/R) Description TX_CLK to PMD Output Pair Deassertion Notes 100BASE-TX mode IDLE IDLE Min Typ 5 Max Units bits Note: Deassertion is determined by measuring the time from the first rising edge of TX_CLK occurring after the deassertion of TX_EN to the first bit of the “T” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100 Mb/s mode.
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DP83849I 8.2.8 100BASE-TX Transmit Timing (tR/F & Jitter) T2.8.1 +1 rise 90% 10% PMD Output Pair 10% +1 fall 90% T2.8.1 -1 fall -1 rise T2.8.1 T2.8.1 T2.8.2 PMD Output Pair eye pattern Parameter T2.8.1 T2.8.2 T2.8.2 Description Notes Min Typ Max Units 3 4 5 ns 100 Mb/s tR and tF Mismatch 500 ps 100 Mb/s PMD Output Pair Transmit Jitter 1.
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DP83849I 8.2.9 100BASE-TX MII Receive Packet Latency Timing PMD Input Pair IDLE Data (J/K) T2.9.1 CRS T2.9.2 RXD[3:0] RX_DV RX_ER Parameter Description Notes Min Typ Max Units T2.9.1 Carrier Sense ON Delay 100BASE-TX mode 20 bits T2.9.2 Receive Data Latency 100BASE-TX mode 24 bits Note: Carrier Sense On Delay is determined by measuring the time from the first bit of the “J” code group to the assertion of Carrier Sense.
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DP83849I 8.2.11 10 Mb/s MII Transmit Timing T2.11.1 T2.11.1 TX_CLK T2.11.3 T2.11.2 TXD[3:0] TX_EN Parameter Valid Data Description Notes Min Typ Max Units 200 210 T2.11.1 TX_CLK High/Low Time 10 Mb/s MII mode 190 ns T2.11.2 TXD[3:0], TX_EN Data Setup to TX_CLK fall 10 Mb/s MII mode 25 ns T2.11.3 TXD[3:0], TX_EN Data Hold from TX_CLK rise 10 Mb/s MII mode 0 ns Note: An attached Mac should drive the transmit signals using the positive edge of TX_CLK.
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DP83849I 8.2.13 10 Mb/s Serial Mode Transmit Timing T2.13.2 T2.13.1 TX_CLK T2.13.4 T2.13.3 TXD[0] TX_EN Parameter Valid Data Min Typ T2.13.1 TX_CLK High Time Description 10 Mb/s Serial mode Notes 20 25 Max Units 30 ns T2.13.2 TX_CLK Low Time 10 Mb/s Serial mode 70 75 80 ns T2.13.3 TXD_0, TX_EN Data Setup to TX_CLK rise 10 Mb/s Serial mode 25 ns T2.13.4 TXD_0, TX_EN Data Hold from TX_CLK rise 10 Mb/s Serial mode 0 ns 8.2.14 10 Mb/s Serial Mode Receive Timing T2.14.1 T2.
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DP83849I 8.2.15 10BASE-T Transmit Timing (Start of Packet) TX_CLK TX_EN TXD T2.15.2 PMD Output Pair T2.15.1 Parameter Description T2.15.1 Notes Transmit Output Delay from the Min Typ Max Units 10 Mb/s MII mode 3.5 bits 10 Mb/s Serial mode 3.5 bits Falling Edge of TX_CLK T2.15.2 Transmit Output Delay from the Rising Edge of TX_CLK Note: 1 bit time = 100 ns in 10Mb/s. 8.2.16 10BASE-T Transmit Timing (End of Packet) TX_CLK TX_EN 0 PMD Output Pair T2.16.1 0 T2.16.
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DP83849I 8.2.17 10BASE-T Receive Timing (Start of Packet) 1st SFD bit decoded 1 0 1 0 1 0 1 0 1 0 1 1 TPRD± T2.17.1 CRS RX_CLK T2.17.2 RX_DV T2.17.3 0000 RXD[3:0] Parameter Preamble Description SFD Notes Min Data Typ Max Units 1000 ns T2.17.1 Carrier Sense Turn On Delay (PMD Input Pair to CRS) 630 T2.17.2 RX_DV Latency 10 bits T2.17.
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DP83849I 8.2.19 10 Mb/s Heartbeat Timing TX_EN TX_CLK T2.19.2 T2.19.1 COL Parameter Description Notes Min Typ Max Units T2.19.1 CD Heartbeat Delay 10 Mb/s half-duplex mode 1200 ns T2.19.2 CD Heartbeat Duration 10 Mb/s half-duplex mode 1000 ns 8.2.20 10 Mb/s Jabber Timing TXE T2.20.1 T2.20.2 PMD Output Pair COL Parameter Description Notes Min Typ Max Units T2.20.1 Jabber Activation Time 85 ms T2.20.2 Jabber Deactivation Time 500 ms www.national.
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DP83849I 8.2.21 10BASE-T Normal Link Pulse Timing T2.21.2 T2.21.1 Normal Link Pulse(s) Parameter Description Notes Min Typ Max Units T2.21.1 Pulse Width 100 ns T2.21.2 Pulse Period 16 ms Note: These specifications represent transmit timings. 8.2.22 Auto-Negotiation Fast Link Pulse (FLP) Timing T2.22.2 T2.22.3 T2.22.1 T2.22.1 Fast Link Pulse(s) clock pulse data pulse clock pulse T2.22.5 T2.22.4 FLP Burst Parameter FLP Burst Description Notes Min Typ Max Units T2.22.
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DP83849I 8.2.23 100BASE-TX Signal Detect Timing PMD Input Pair T2.23.1 T2.23.2 SD+ internal Parameter Description Notes Min Typ Max Units T2.23.1 SD Internal Turn-on Time 1 ms T2.23.2 SD Internal Turn-off Time 350 µs Max Units 240 ns Note: The signal amplitude on PMD Input Pair must be TP-PMD compliant. 8.2.24 100 Mb/s Internal Loopback Timing TX_CLK TX_EN TXD[3:0] CRS T2.24.1 RX_CLK RX_DV RXD[3:0] Parameter T2.24.
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DP83849I 8.2.25 10 Mb/s Internal Loopback Timing TX_CLK TX_EN TXD[3:0] CRS T2.25.1 RX_CLK RX_DV RXD[3:0] Parameter T2.25.1 Description TX_EN to RX_DV Loopback Notes Min 10 Mb/s internal loopback mode Typ Max Units 2 µs Note: Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN. 99 www.national.
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DP83849I 8.2.26 RMII Transmit Timing T2.26.1 X1 T2.26.2 TXD[1:0] TX_EN T2.26.3 Valid Data T2.26.4 PMD Output Pair Parameter Symbol Description Notes Min X1 Clock Period T2.26.2 TXD[1:0], TX_EN, Data Setup to X1 rising 4 ns T2.26.3 TXD[1:0], TX_EN, Data Hold from X1 rising 2 ns T2.26.4 X1 Clock to PMD Output Pair 100BASE-TX mode Latency (100Mb) 100 20 Max Units T2.26.1 www.national.
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DP83849I 8.2.27 RMII Receive Timing PMD Input Pair IDLE Data (J/K) Data (TR) T2.27.4 T2.27.5 X1 T2.27.1 T2.27.2 T2.27.3 T2.27.2 T2.27.2 RX_DV CRS_DV T2.27.2 RXD[1:0] RX_ER Parameter Description Notes Min 50 MHz Reference Clock Typ Max 20 Units T2.27.1 X1 Clock Period T2.27.2 RXD[1:0], CRS_DV, RX_DV and RX_ER output delay from X1 rising T2.27.3 CRS ON delay (100Mb) 100BASE-TX mode 18.5 bits T2.27.4 CRS OFF delay (100Mb) 100BASE-TX mode 27 bits T2.27.
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DP83849I 8.2.28 Single Clock MII (SCMII) Transmit Timing T2.28.1 X1 T2.28.2 TXD[3:0] TX_EN T2.28.3 Valid Data T2.28.4 PMD Output Pair Parameter Symbol Description Notes Min Typ Units X1 Clock Period 25MHz Reference Clock T2.28.2 TXD[3:0], TX_EN Data Setup To X1 rising 4 ns T2.28.3 TXD[3:0], TX_EN Data Hold From X1 rising 2 ns T2.28.4 X1 Clock to PMD Output Pair Latency (100Mb) 100BASE-TX mode Note: Latency measurement is made from the X1 Rising edge to the first bit of symbol.
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DP83849I 8.2.29 Single Clock MII (SCMII) Receive Timing PMD Input Pair IDLE (J/K) Data Data (TR) T2.29.4 T2.29.5 X1 T2.29.1 T2.29.3 CRS T2.29.2 T2.29.2 RX_DV RXD[1:0] RX_ER Parameter Description Notes Min 25MHz Reference Clock Typ Max 40 Units T2.29.1 X1 Clock Period T2.29.2 RXD[3:0], RX_DV and RX_ER From X1 rising output delay T2.29.3 CRS ON delay (100Mb) 100BASE-TX mode 19 bits T2.29.4 CRS OFF delay (100Mb) 100BASE-TX mode 26 bits T2.29.
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DP83849I 8.2.30 Isolation Timing Clear bit 10 of BMCR (return to normal operation from Isolate mode) T2.30.1 MODE NORMAL ISOLATE Parameter T2.30.1 Description Notes Min Typ From software clear of bit 10 in the BMCR register to the transition from Isolate to Normal Mode Max Units 100 µs Max Units 8.2.31 CLK2MAC Timing X1 T2.31.2 T2.31.1 T2.31.1 CLK2MAC Parameter T2.31.1 T2.31.
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DP83849I 8.2.32 100 Mb/s X1 to TX_CLK Timing X1 T2.32.1 TX_CLK Parameter T2.32.1 Description X1 to TX_CLK delay Notes 100 Mb/s Normal mode Min 0 Typ Max Units 5 ns Note: X1 to TX_CLK timing is provided to support devices that use X1 instead of TX_CLK as the reference for transmit Mll data. 105 www.national.
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DP83849I PHYTER® DUAL Industrial Temperature with Flexible Port Switching Dual Port 10/100 Mb/s Ethernet Physical Layer Transceiver 9.0 Physical Dimensions inches (millimeters) unless otherwise noted Thin Quad Flat Package (TQFP) NS Package Number VHB80A THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PROCUCTS.
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