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correction

C I/F

REG

Back-EMF

detection

ROM

Gate

drive

Gate

drive

Control and

playback

engine

LRA

ERM

OUT±

OUT+

GND

REG

IN/TRIG

SDA

SCL

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DRV2605

SLOS825C –DECEMBER 2012–REVISED SEPTEMBER 2014

DRV2605 Haptic Driver for ERM and LRA With Built-In Library and Smart-Loop

Architecture

The DRV2605 device provides an extensive

1 Features

integrated library over 100 licensed effects from

• Flexible Haptic/Vibra Driver

Immersion for ERM and LRA which eliminates the

– LRA (Linear Resonance Actuator)

need to design haptics waveforms.

– ERM (Eccentric Rotating Mass)

The DRV2605 device offers a licensed version of the

• I

C Controlled Digital Playback Engine

TouchSense 2200 software from Immersion, which

includes the 2200 Effects Library, and 2200 audio-to-

– Real-Time Playback Mode via I

vibe features. Additionally, the real-time playback

• Smart Loop Architecture

(1)

mode allows the host processor to bypass the library

– Automatic Overdrive/Braking (ERM/LRA)

playback engine and play waveforms directly from the

host through I

– Automatic Resonance Tracking (LRA)

– Automatic Actuator Diagnostic (ERM/LRA)

The DRV2605 device also contains a smart-loop

architecture, which allows effortless auto resonant

– Automatic Level Calibration (ERM/LRA)

drive for LRA as well as feedback-optimized ERM

• Licensed Immersion™ TouchSense

2200

drive. This feedback provides automatic overdrive

features:

and braking, which creates a simplified input

– Integrated Immersion Effect Library

waveform paradigm as well as reliable motor control

and consistent motor performance. The audio-to-

– Audio to Vibe

haptics mode automatically converts an audio input

• Optional PWM Input with 0% to 100% Duty Cycle

signal to meaningful haptic effects.

Control Range

The DRV2605 device features a trinary-modulated

• Optional Analog Input Control

output stage, providing greater efficiency than linear-

• Optional Hardware Trigger Pin

based output drivers. The 9-ball WCSP footprint,

• Efficient Output Drive

flexible operation, and low component count make

the DRV2605 device the ideal choice for portable and

• Fast Start Up Time

touch-enabled vibratory and haptic applications.

• Constant Acceleration Over Supply Voltage

For an important notice regarding Immersion

• 1.8 V Compatible, VDD Tolerant Digital Pins

software, see the Legal Notice section.

(1)

Patent pending control algorithm

Device Information

(1)

2 Applications

PART NUMBER PACKAGE BODY SIZE (MAX)

• Mobile Phones and Tablets

DRV2605 DSBGA (9) 1.50 mm × 1.50 mm

• Watches and Wearable Technology

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

• Remote Controls, Mice, and Peripheral Devices

• Touch-Enabled Devices

• Human-Machine Interfaces

3 Description

The DRV2605 device is designed to provide

extremely-flexible haptic control of ERM and LRA

actuators over a shared I

C-compatible bus. This

control relieves the host processor from ever

generating pulse-width modulated (PWM) drive

signals, saving both costly timer interrupts and

hardware pins.

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

Summary of content (62 pages)

PAGE 1
Product Folder Sample & Buy Tools & Software Technical Documents Support & Community DRV2605 SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 DRV2605 Haptic Driver for ERM and LRA With Built-In Library and Smart-Loop Architecture 1 Features • 1 • • • • • • • • • • (1) Flexible Haptic/Vibra Driver – LRA (Linear Resonance Actuator) – ERM (Eccentric Rotating Mass) I2C Controlled Digital Playback Engine – Real-Time Playback Mode via I2C Smart Loop Architecture(1) – Automatic Overdrive/Braking (ERM/L
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DRV2605 SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications..........................................
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DRV2605 www.ti.com SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 Changes from Original (December 2012) to Revision A • Page Changed |IIH| MAX value from 3 to 3.5µA per CMS #C1303020 ...........................................................................................
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DRV2605 SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 www.ti.com 5 Pin Configuration and Functions YZF Package 9-Pin DSBGA With 0,5-mm Pitch (Top View) A EN REG OUT+ B IN/TRIG SDA GND C SCL VDD OUT± 1 2 3 Pin Functions PIN TYPE (1) DESCRIPTION NO. NAME A1 EN I Device enable A2 REG O The REG pin is the 1.8-V regulator output. A 1-µF capacitor is required. A3 OUT+ O Positive haptic driver differential output B1 IN/TRIG I Multi-mode Input.
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DRV2605 www.ti.com SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range, TA = 25°C (unless otherwise noted) Input voltage MIN MAX UNIT VDD –0.3 6 V EN –0.3 VDD + 0.3 V SDA –0.3 VDD + 0.3 V SCL –0.3 VDD + 0.3 V IN/TRIG –0.3 VDD + 0.3 V Operating free-air temperature range, TA –40 85 °C Operating junction temperature range, TJ –40 150 °C 6.
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DRV2605 SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 www.ti.com 6.5 Electrical Characteristics TA = 25°C, VDD = 3.6 V (unless otherwise noted) PARAMETER V(REG) Voltage at the REG pin IIL Digital low-level input current IIH Digital high-level input current TEST CONDITIONS MIN TYP MAX 1.84 V EN VDD = 5.5 V , VI = 0 V 1 IN/TRIG, SDA, SCL VDD = 5.5 V, VI = VDD 1 EN VDD = 5.5 V, VI = VDD 3.5 0.
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DRV2605 www.ti.com SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 tw(H) tw(L) SCL tsu(1) th(1) SDA Figure 1. SCL and SDA Timing SCL tsu(2) tsu(3) th(2) t(BUF) SDA Start Condition Stop Condition Figure 2. Timing for Start and Stop Conditions 6.8 Typical Characteristics IN/TRIG Acceleration [OUT+] − [OUT−] (Filtered) Voltage (2V/div) Voltage (2V/div) IN/TRIG Acceleration [OUT+] − [OUT−] (Filtered) 0 40m VDD = 3.
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DRV2605 SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 www.ti.com Typical Characteristics (continued) Voltage (2V/div) SDA Acceleration [OUT+] − [OUT−] (Filtered) Voltage (2V/div) SDA Acceleration [OUT+] − [OUT−] (Filtered) 0 200m 400m 600m Time (s) VDD = 3.6 V Sequence = 0x01, 0x48 800m 1 ERM open loop Internal trigger 0 200m 400m 600m Time (s) VDD = 3.6 V Transition click 1 - 100% Figure 5. ERM Click-Bounce (ROM) 800m 1 LRA closed loop Internal trigger Figure 6.
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DRV2605 www.ti.com SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 7 Detailed Description 7.1 Overview The DRV2605 device is a haptic driver that relies on the back-EMF produced by an actuator to provide a closedloop system that offers extremely flexible control of LRA and ERM actuators over a shared I2C-compatible bus or PWM input signal. This schema helps improve actuator performance in terms of acceleration consistency, start time, and brake time.
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DRV2605 SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 www.ti.com 7.3 Feature Description 7.3.1 Support for ERM and LRA Actuators The DRV2605 device supports both ERM and LRA actuators. The ERM_LRA bit in register 0x1A must be configured to select the type of actuator that the device uses. 7.3.2 Smart-Loop Architecture The smart-loop architecture is an advanced closed-loop system that optimizes the performance of the actuator and allows for failure detection.
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DRV2605 www.ti.com SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 Feature Description (continued) Ideal Open-Loop Waveform for Motor A Ideal Open-Loop Waveform for Motor B Same simple input for both motors Input and output Feedback provides optimum output drive Accleration Output with feedback Figure 11. Waveform Simplification With Smart Loop 7.3.2.3.
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DRV2605 SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 www.ti.com Feature Description (continued) 7.3.2.4.1 Automatic Compensation for Resistive Losses The DRV2605 device automatically compensates for resistive losses in the driver. During the automatic levelcalibration routine, the impedance of the actuator is checked and the compensation factor is determined and stored in the A_CAL_COMP[7:0] bit. 7.3.2.4.
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DRV2605 www.ti.com SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 Feature Description (continued) For the LRA, the DRV2605 device automatically tracks the resonance frequency unless the LRA_OPEN_LOOP bit in register 0x1D is set. If the LRA_OPEN_LOOP bit is set, the LRA is driven according to the frequency of the PWM input signal. Specifically, the driving frequency is the PWM frequency divided by 128. 7.3.5.
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DRV2605 SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 www.ti.com The time values are additive offsets and are 8-bit signed values. The default offset of these values is 0. Positive values add and negative values subtract from the time value of the effect that is currently played. The most positive value in the waveform is automatically interpreted as the overdrive time, and the most negative value in the waveform is automatically interpreted as the brake time.
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DRV2605 www.ti.com SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 NOTE The triggered effect must already be selected to take advantage of the lower latency. This option works best for accelerating a pre-queued high-priority effect (such as a button press) or for the repeated firing of the same effect (such as scrolling). 7.3.5.6.1 I2C Trigger Setting the GO bit (in register 0x0C) launches the waveform. The user can cancel the launching of the waveform by clearing the GO bit. 7.3.5.6.
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DRV2605 SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 www.ti.com 7.3.6 Edge Rate Control The DRV2605 output driver implements edge rate control (ERC). This control ensures that the rise and fall characteristics of the output drivers do not emit levels of radiation that could interfere with other circuitry common in mobile and portable platforms. Because of ERC most system do not require external output filters, capacitors, or ferrites beads. 7.3.
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DRV2605 www.ti.com SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 Device Functional Modes (continued) EN = 0 EN = 1 Shutdown Standby STANDBY = 0 EN = 0 STANDBY = 1 Active DEV_RESET = 1 Figure 15. Power-State Transition Diagram 7.4.1.1 Operation With VDD < 2.5 V (Minimum VDD) Operating the device with a VDD value below 2 V is not recommended. 7.4.1.2 Operation With VDD > 6 V (Absolute Maximum VDD) The DRV2605 device is designed to operate at up to 5.5 V, with an absolute maximum voltage of 6 V .
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DRV2605 SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 www.ti.com Device Functional Modes (continued) Change Modes Ready GO Signal = 1 Process Done GO Signal = 1 Optional Run Process Check for Output Shorts No Short Wait 1 s Short Found Short Found Note: If an output short is present before a waveform is played, changing modes (with the MODE[2:0] bit in register 0x01) is required to resume normal playback. Figure 16. Diagram of Active States 7.4.
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DRV2605 www.ti.com SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 Also accessible 2 (R/W) through I C MODE[2:0] = 1 (External trigger ² edge) MODE[2:0] = 2 (External trigger ² level) GO Bit IN/TRIG (Trigger) GO Bit MODE[2:0] = 3 (PWM and analog input) GO Signal MODE[2:0] = 4 (Audio-to-haptics) MODE[2:0] = 5 (RTP mode) Figure 17. GO-Signal Logic 7.4.
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DRV2605 SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 www.ti.com 7.5 Programming 7.5.1 Auto-Resonance Engine Programming for the LRA 7.5.1.1 Drive-Time Programming The resonance frequency of each LRA actuator varies based on many factors and is generally dominated by mechanical properties. The auto-resonance engine-tracking system is optimized by providing information about the resonance frequency of the actuator. The DRIVE_TIME[4:0] bit is used as an initial guess for the half-period of the LRA..
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DRV2605 www.ti.com SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 Programming (continued) 7.5.2.2 Overdrive Voltage-Clamp Programming During closed-loop operation, the actuator feedback allows the output voltage go above the rated voltage during the automatic overdrive and automatic braking periods. The OD_CLAMP[7:0] bit (in Register 0x17) sets a clamp so that the automatic overdrive is bounded. The OD_CLAMP[7:0] bit also serves as the full-scale reference voltage for open-loop operation.
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DRV2605 SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 www.ti.com Programming (continued) 7-bit slave address R/W A b7 b6 b5 b4 b3 b2 b 1 b 0 8-bit register data for address (N) A 8-bit register address (N) b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 A 8-bit register data for address (N) A b7 b6 b5 b4 b3 b2 b1 b0 Start Stop Figure 18. Typical I2C Sequence The DRV2605 device operates as an I2C-slave 1.8-V logic thresholds, but can operate up to the VDD voltage.
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DRV2605 www.ti.com SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 Programming (continued) 7.5.3.5 Multiple-Byte Write and Incremental Multiple-Byte Write A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes are transmitted by the master device to the DRV2605 device as shown in Figure 20. After receiving each data byte, the DRV2605 device responds with an acknowledge bit.
PAGE 24
DRV2605 SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 www.ti.com Programming (continued) 7.5.4 Programming for Open-Loop Operation The DRV2605 device can be used in open-loop mode and closed-loop mode. If open-loop operation is desired, the first step is to determine which actuator type is to use, either ERM or LRA. 7.5.4.
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DRV2605 www.ti.com SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 Programming (continued) The following instructions list the step-by-step register configuration for auto-calibration. For additional details see the Register Map section. 1. Apply the supply voltage to the DRV2605 device, and pull the EN pin high. The supply voltage should allow for adequate drive voltage of the selected actuator. 2. Write a value of 0x07 to register 0x01.
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DRV2605 SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 www.ti.com Programming (continued) 7.5.8 Waveform Playback Programming 7.5.8.1 Data Formats for Waveform Playback The DRV2605 smart-loop architecture has three modes of operation. Each of these modes can drive either ERM or LRA devices. 1. Open-loop mode 2. Closed-loop mode (unidirectional) 3. Closed-loop mode (bidirectional) Each mode has different advantages and disadvantages.
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DRV2605 www.ti.com SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 Programming (continued) 7.5.8.1.2 Closed-Loop Mode, Unidirectional In closed-loop unidirectional mode, the DRV2605 device provides automatic overdrive and braking for both ERM and LRA devices. This mode is the most easy mode to use and understand. This mode uses the full 8-bit resolution of the driver.
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DRV2605 SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 www.ti.com Programming (continued) 7.5.8.1.3 Closed-Loop Mode, Bidirectional In closed-loop bidirectional mode, the DRV2605 device provides automatic overdrive and braking for both ERM and LRA devices. This mode preserves compatibility with data created in open-loop signaling by maintaining zero drive-strength at the mid-scale value.
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DRV2605 www.ti.com SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 Programming (continued) 7.5.8.2 Waveform Setup and Playback Playback of a haptic effect can occur in multiple ways. Using the PWM mode, RTP mode, audio-to-vibe mode, and analog-input mode can provide the waveform in real time. The waveforms can also be played from the ROM in which case the waveform playback engine is used and the waveform is either played by an internal GO bit (register 0x0C), or by an external trigger. 7.5.8.2.
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DRV2605 SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 www.ti.com Programming (continued) GO Waveform Sequencer ROM Library WAV_FRM_SEQ0[7:0] Effect 1 WAV_FRM_SEQ1[7:0] Effect 2 WAV_FRM_SEQ2[7:0] Effect 3 WAV_FRM_SEQ3[7:0] Effect 4 WAV_FRM_SEQ4[7:0] Effect 5 WAV_FRM_SEQ5[7:0] WAV_FRM_SEQ6[7:0] WAV_FRM_SEQ7[7:0] Effect 123 Figure 27. Waveform Sequencer Programming 7.5.8.2.
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DRV2605 www.ti.com SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 7.6 Register Map Table 3. Register Map Overview REG NO.
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DRV2605 SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 www.ti.com 7.6.1 Status (Address: 0x00) Figure 28. Status Register 7 RO-0 6 DEVICE_ID[2:0] RO-1 5 4 Reserved RO-1 3 DIAG_RESULT RO-0 2 FB_STS RO-0 1 OVER_TEMP RO-0 0 OC_DETECT RO-0 Table 4. Status Register Field Descriptions BIT FIELD TYPE DEFAULT DESCRIPTION 7-5 DEVICE_ID[2:0] RO 3 Device identifier. The DEVICE_ID bit indicates the part number to the user.
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DRV2605 www.ti.com SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 7.6.2 Mode (Address: 0x01) Figure 29. Mode Register 7 DEV_RESET R/W-0 6 STANDBY R/W-1 5 4 Reserved 3 2 1 MODE[2:0] R/W-0 0 Table 5. Mode Register Field Descriptions BIT FIELD TYPE DEFAULT DESCRIPTION 7 DEV_RESET R/W 0 Device reset. Setting this bit performs the equivalent operation of power cycling the device. Any playback operations are immediately interrupted, and all registers are reset to the default values.
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DRV2605 SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 www.ti.com 7.6.3 Real-Time Playback Input (Address: 0x02) Figure 30. Real-Time Playback Input Register 7 6 5 4 3 RTP_INPUT[7:0] R/W-0 2 1 0 Table 6. Real-Time Playback Input Register Field Descriptions BIT FIELD TYPE DEFAULT DESCRIPTION 7-0 RTP_INPUT[7:0] R/W 0 This field is the entry point for real-time playback (RTP) data. The DRV2605 playback engine drives the RTP_INPUT[7:0] value to the load when MODE[2:0] = 5 (RTP mode).
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DRV2605 www.ti.com SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 7.6.5 Waveform Sequencer (Address: 0x04 to 0x0B) Figure 32. Waveform Sequencer Register 7 WAIT R/W-0 6 5 4 3 WAV_FRM_SEQ[6:0] R/W-0 2 1 0 Table 8. Waveform Sequencer Register Field Descriptions BIT FIELD TYPE DEFAULT DESCRIPTION 7 WAIT R/W 0 When this bit is set, the WAV_FRM_SEQ[6:0] bit is interpreted as a wait time in which the playback engine idles.
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DRV2605 SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 www.ti.com 7.6.7 Overdrive Time Offset (Address: 0x0D) Figure 34. Overdrive Time Offset Register 7 6 5 4 3 2 1 0 ODT[7:0] R/W-0 Table 10. Overdrive Time Offset Register Field Descriptions BIT FIELD TYPE DEFAULT DESCRIPTION 7-0 ODT R/W 0 This bit adds a time offset to the overdrive portion of the library waveforms.
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DRV2605 www.ti.com SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 7.6.9 Sustain Time Offset, Negative (Address: 0x0F) Figure 36. Sustain Time Offset, Negative Register 7 6 5 4 3 2 1 0 SNT[7:0] R/W-0 Table 12. Sustain Time Offset, Negative Register Field Descriptions BIT FIELD TYPE DEFAULT DESCRIPTION 7-0 SNT R/W 0 This bit adds a time offset to the negative sustain portion of the library waveforms.
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DRV2605 SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 www.ti.com 7.6.11 Audio-to-Vibe Control (Address: 0x11) Figure 38. Audio-to-Vibe Control Register 7 6 5 4 3 2 ATH_PEAK_TIME[1:0] R/W-0 R/W-1 Reserved 1 0 ATH_FILTER[1:0] R/W-0 R/W-1 Table 14.
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DRV2605 www.ti.com SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 7.6.14 Audio-to-Vibe Minimum Output Drive (Address: 0x14) Figure 41. Audio-to-Vibe Minimum Output Drive Register 7 6 5 R/W-0 R/W-0 R/W-0 4 3 ATH_MIN_DRIVE[7:0] R/W-1 R/W-1 2 1 0 R/W-0 R/W-0 R/W-1 Table 17.
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DRV2605 SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 www.ti.com 7.6.17 Overdrive Clamp Voltage (Address: 0x17) Figure 44. Overdrive Clamp Voltage Register 7 6 5 R/W-1 R/W-0 R/W-0 4 3 OD_CLAMP[7:0] R/W-1 R/W-1 2 1 0 R/W-0 R/W-0 R/W-1 Table 20.
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DRV2605 www.ti.com SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 7.6.20 Feedback Control (Address: 0x1A) Figure 47. Feedback Control Register 7 N_ERM_LRA R/W-0 6 5 4 FB_BRAKE_FACTOR[2:0] R/W-0 R/W-1 R/W-1 3 2 LOOP_GAIN[1:0] R/W-0 R/W-1 1 0 BEMF_GAIN[1:0] R/W-1 R/W-0 Table 23. Feedback Control Register Field Descriptions BIT FIELD TYPE DEFAULT DESCRIPTION 7 N_ERM_LRA R/W 0 This bit sets the DRV2605 device in ERM or LRA mode. This bit should be set prior to running auto calibration.
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DRV2605 SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 www.ti.com 7.6.21 Control1 (Address: 0x1B) Figure 48. Control1 Register 7 STARTUP_BO OST R/W-1 6 Reserved 5 AC_COUPLE 4 3 2 DRIVE_TIME[4:0] 1 0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-1 Table 24. Control1 Register Field Descriptions BIT FIELD TYPE DEFAULT DESCRIPTION 7 STARTUP_BOOST R/W 1 This bit applies higher loop gain during overdrive to enhance actuator transient response.
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DRV2605 www.ti.com SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 7.6.22 Control2 (Address: 0x1C) Figure 49. Control2 Register 7 BIDIR_INPUT R/W-1 6 BRAKE_STABI LIZER R/W-1 5 4 SAMPLE_TIME[1:0] 3 2 BLANKING_TIME[1:0] R/W-1 R/W-0 1 0 IDISS_TIME[1:0] R/W-1 R/W-0 R/W-1 Table 25. Control2 Register Field Descriptions BIT FIELD TYPE DEFAULT DESCRIPTION 7 BIDIR_INPUT R/W 1 The BIDIR_INPUT bit selects how the engine interprets data.
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DRV2605 SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 www.ti.com 7.6.23 Control3 (Address: 0x1D) Figure 50. Control3 Register 7 6 NG_THRESH[1:0] R/W-1 R/W-0 5 ERM_OPEN_L OOP R/W-1 4 SUPPLY_COM P_DIS R/W-0 3 2 1 DATA_FORMA LRA_DRIVE_M N_PWM_ANAL T_RTP ODE OG R/W-0 R/W-0 R/W-0 0 LRA_OPEN_L OOP R/W-0 Table 26. Control3 Register Field Descriptions BIT 7-6 FIELD NG_THRESH[1:0] TYPE R/W DEFAULT 1 DESCRIPTION This bit is the noise-gate threshold for PWM and analog inputs.
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DRV2605 www.ti.com SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 7.6.24 Control4 (Address: 0x1E) Figure 51. Control4 Register 7 6 5 4 AUTO_CAL_TIME[1:0] Reserved R/W-1 3 Reserved R/W-0 2 OTP_STATUS R-0 1 Reserved 0 OTP_PROGRA M R/W-0 Table 27. Control4 Register Field Descriptions BIT FIELD 7-6 Reserved 5-4 AUTO_CAL_TIME[1:0] TYPE DEFAULT DESCRIPTION R/W 2 This bit sets the length of the auto calibration time.
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DRV2605 SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 www.ti.com 7.6.25 V(BAT) Voltage Monitor (Address: 0x21) Figure 52. V(BAT) Voltage-Monitor Register 7 6 5 4 3 2 1 0 VBAT[7:0] R/W-0 Table 28. V(BAT) Voltage-Monitor Register Field Descriptions BIT FIELD TYPE DEFAULT DESCRIPTION 7-0 VBAT[7:0] R/W 0 This bit provides a real-time reading of the supply voltage at the VDD pin. The device must be actively sending a waveform to take a reading. VDD (V) = VBAT[7:0] × 5.6V / 255 7.6.
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DRV2605 www.ti.com SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.
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DRV2605 SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 www.ti.com 8.2 Typical Application A typical application of the DRV2605 device is in a system that has external buttons which fire different haptic effects when pressed. Figure 56 shows a typical schematic of such a system. The buttons can be physical buttons, capacitive-touch buttons, or GPIO signals coming from the touch-screen system. Effects in this type of system are programmable. TPS73633 OUT NR/FB IN EN GND C(LDO) 1 µF R(PU) 2.
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DRV2605 www.ti.com SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 IL IL OUT+ OUT+ + Motor-spin direction ± Motor-spin direction VO VO + ± OUT± OUT± IL IL Figure 57. Motor Spin Direction in ERM Motors Another common approach to driving DC motors is the concept of overdrive voltage. To overcome the inertia of the mass of the motor, these motors are often overdriven for a short amount of time before returning to the rated voltage of the motor to sustain the rotation of the motor.
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DRV2605 SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 www.ti.com 8.2.2.3 Interface Selection The I2C interface is required to configure the device. The device can be used fully with this interface and with either RTP or internal memory. The advantage of using this interface is that no additional GPIO (for the IN/TRIG pin) is required for firing effects, and no PWM signal is required to be generated. Therefore the IN/TRIG pin can be connected to GND.
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DRV2605 www.ti.com SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 8.3 Initialization Setup 8.3.1 Initialization Procedure 1. 2. 3. 4. 5. 6. 7. 8. After powerup, wait at least 250 µs before the DRV2605 device accepts I2C commands. Assert the EN pin (logic high). The EN pin can be asserted any time during or after the 250 µs wait period. Write the MODE register (address 0x01) to value 0x00 to remove the device from standby mode.
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DRV2605 SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 www.ti.com Initialization Setup (continued) 8.3.2.3 Play a PWM or Analog Input Waveform 1. Initialize the device as shown in the Initialization Procedure section. 2. Assert the EN pin (active high) if it was previously deasserted. 3. If register 0x01 already holds the desired value and the STANDBY bit is low, the user can skip this step. Set the MODE value to 3 (PWM/Analog Mode) at address 0x01.
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DRV2605 www.ti.com SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 10 Layout 10.1 Layout Guidelines Use the following guidelines for the DRV2605 layout: • The decoupling capacitor for the power supply (VDD) should be placed closed to the device pin. • The filtering capacitor for the regulator (REG) should be placed close to the device REG pin. • When creating the pad size for the WCSP pins, TI recommends that the PCB layout use nonsolder maskdefined (NSMD) land.
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DRV2605 SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 www.ti.com 10.1.1 Trace Width The recommended trace width at the solder pins is 75 µm to 100 µm to prevent solder wicking onto wider PCB traces. Maintain this trace width until the pin pattern is escaped then the trace width can be increased for improved current flow. The width and length of the 75-µm to 100-µm traces should be as symmetrical as possible around the device to provide even solder reflow on each of the pins. 10.
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DRV2605 www.ti.com SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 11 Device and Documentation Support 11.
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DRV2605 SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014 www.ti.com Waveform Library Effects List (continued) EFFECT ID NO. WAVEFORM NAME EFFECT ID NO> WAVEFORM NAME EFFECT ID NO.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 4-Feb-2014 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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PACKAGE MATERIALS INFORMATION www.ti.com 18-Aug-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) DRV2605YZFR DSBGA YZF 9 3000 180.0 8.4 DRV2605YZFR DSBGA YZF 9 3000 178.0 DRV2605YZFT DSBGA YZF 9 250 178.0 DRV2605YZFT DSBGA YZF 9 250 180.0 1.65 1.65 0.81 4.0 8.0 Q1 9.2 1.65 1.65 0.81 4.0 8.0 Q1 9.2 1.65 1.65 0.81 4.0 8.0 Q1 8.
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PACKAGE MATERIALS INFORMATION www.ti.com 18-Aug-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) DRV2605YZFR DSBGA YZF 9 3000 182.0 182.0 17.0 DRV2605YZFR DSBGA YZF 9 3000 270.0 225.0 227.0 DRV2605YZFT DSBGA YZF 9 250 270.0 225.0 227.0 DRV2605YZFT DSBGA YZF 9 250 182.0 182.0 17.
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D: Max = 1.47 mm, Min = 1.41 mm E: Max = 1.47 mm, Min = 1.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.