Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - power management - special purpose 4 mA HLQFP 32 (7x7)

ActualSize

9mmSquare

1 µF

AVDD

AGND (Connect to PowerPAD)

ROSC

COSC

AREF

IN+

IN−IN−

FAULT1

FAULT0

PVDD

H/C

PGND

PWM

PVDD

FREQ

120 kΩ

220 pF

1 µF

Shutdown Control

1 kΩ

DC Control

Voltage

10 µF

10 µH

1 µF

FAULT1

FAULT0

To TEC or Laser

Diode Anode

To TEC or Laser

Diode Cathode

1 µF

SHUTDOWN

INT/EXT

DRV593

DRV594

10 µF

DRV593

DRV594

www.ti.com

SLOS401C –OCTOBER 2002–REVISED JULY 2010

±3-A HIGH-EFFICIENCY PWM POWER DRIVER

Check for Samples: DRV593, DRV594

FEATURES

DESCRIPTION

• Operation Reduces Output Filter Size and Cost

by 50% Compared to DRV591

The DRV593 and DRV594 are high-efficiency,

high-current power amplifiers ideal for driving a wide

• ±3-A Maximum Output Current

variety of thermoelectric cooler elements in systems

• Low Supply Voltage Operation: 2.8 V to 5.5 V

powered from 2.8 V to 5.5 V. The operation of the

• High Efficiency Generates Less Heat

device requires only one inductor and capacitor for

• Overcurrent and Thermal Protection the output filter, saving significant printed-circuit

board area. Pulse-width modulation (PWM) operation

• Fault Indicators for Overcurrent, Thermal and

and low output stage on-resistance significantly

Undervoltage Conditions

decrease power dissipation in the amplifier.

• Two Selectable Switching Frequencies

The DRV593 and DRV594 are internally protected

• Internal or External Clock Sync

against thermal and current overloads. Logic-level

• PWM Scheme Optimized for EMI

fault indicators signal when the junction temperature

has reached approximately 128°C to allow for

• 9×9 mm PowerPAD™ Quad Flatpack Package

system-level shutdown before the amplifier's internal

thermal shutdown circuitry activates. The fault

APPLICATIONS

indicators also signal when an overcurrent event has

• Thermoelectric Cooler (TEC) Driver

occurred. If the overcurrent circuitry is tripped, the

• Laser Diode Biasing

devices automatically reset (see application

information section for more details).

The PWM switching frequency may be set to 500 kHz

or 100 kHz depending on system requirements. To

eliminate external components, the gain is fixed at

2.3 V/V for the DRV593. For the DRV594, the gain is

fixed at 14.5 V/V.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (26 pages)

PAGE 1
Actual Size 9mm Square DRV593 DRV594 www.ti.com SLOS401C – OCTOBER 2002 – REVISED JULY 2010 ±3-A HIGH-EFFICIENCY PWM POWER DRIVER Check for Samples: DRV593, DRV594 FEATURES 1 • 2 • • • • • • • • • DESCRIPTION Operation Reduces Output Filter Size and Cost by 50% Compared to DRV591 ±3-A Maximum Output Current Low Supply Voltage Operation: 2.8 V to 5.
PAGE 2
DRV593 DRV594 SLOS401C – OCTOBER 2002 – REVISED JULY 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
PAGE 3
DRV593 DRV594 www.ti.com SLOS401C – OCTOBER 2002 – REVISED JULY 2010 ELECTRICAL CHARACTERISTICS over operating free-air temperature range unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX 14 UNIT |VOO| Output offset voltage (measured differentially) VI = VDD/2, IO = 0 A 100 mV |IIH| High-level input current VDD = 5.5V, VI = VDD 1 mA |IIL| Low-level input current VDD = 5.
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DRV593 DRV594 SLOS401C – OCTOBER 2002 – REVISED JULY 2010 www.ti.com PIN ASSIGNMENTS FREQ INT/EXT PVDD PVDD PVDD PWM PWM PWM VFP PACKAGE (TOP VIEW) 32 31 30 29 28 27 26 25 AVDD AGND ROSC COSC AREF IN+ IN− SHUTDOWN 1 24 2 23 22 3 4 PowerPAD 5 6 PWM PGND PGND PGND PGND PGND PGND H/C 21 20 19 18 7 17 8 FAULT1 FAULT0 PVDD PVDD PVDD H/C H/C H/C 9 10 11 12 13 14 15 16 TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME NO.
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DRV593 DRV594 www.ti.com SLOS401C – OCTOBER 2002 – REVISED JULY 2010 FUNCTIONAL BLOCK DIAGRAM AVDD AGND AVDD R IN− 2.3 x R (DRV593) 14.5 x R (DRV594) _ + PVDD + _ Gate Drive H/C _ + _ + + _ PGND PVDD IN+ R + _ 2.3 x R (DRV593) 14.
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DRV593 DRV594 SLOS401C – OCTOBER 2002 – REVISED JULY 2010 www.ti.com TEST SETUP FOR GRAPHS The LC output filter used in Figure 2, Figure 3, Figure 8, and Figure 9 is shown below. L1 PWM C1 RL H/C L1 = 10 µH (part number: CDRH104R, manufacturer: Sumida) C1 = 10 µF (part number: ECJ-4YB1C106K, manufacturer: Panasonic) Figure 1. LC Output Filter EFFICIENCY vs LOAD RESISTANCE EFFICIENCY vs LOAD RESISTANCE 100 100 90 90 PO = 2 W 80 80 PO = 0.5 W PO = 1 W 70 PO = 0.
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DRV593 DRV594 www.ti.com SLOS401C – OCTOBER 2002 – REVISED JULY 2010 DRAIN-SOURCE ON-STATE RESISTANCE vs SUPPLY VOLTAGE DRAIN-SOURCE ON-STATE RESISTANCE vs FREE-AIR TEMPERATURE 300 rDS(on) − Drain-Source On-State Resistance − mΩ IO = 1 A TA = 25°C 250 Total 200 150 Low Side 100 High Side 50 0 2.7 3.1 3.5 3.9 4.3 4.7 VDD − Supply Voltage − V 5.1 5.5 200 Total 150 Low Side 100 High Side 50 0 −40 −15 10 35 60 TA − Free-Air Temperature − °C Figure 5.
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DRV593 DRV594 SLOS401C – OCTOBER 2002 – REVISED JULY 2010 www.ti.com POWER SUPPLY REJECTION RATIO vs FREQUENCY POWER SUPPLY REJECTION RATIO vs FREQUENCY −20 −40 −50 −60 −70 −80 10 100 1k 10k f − Frequency − Hz −30 −40 −50 −60 −70 −80 10 100k 100 1k 10k f − Frequency − Hz Figure 8. Figure 9. DRV593 CLOSED LOOP RESPONSE DRV594 CLOSED LOOP RESPONSE 4 Phase 3 10 16 0 14 −10 12 −40 Gain − V/V −30 2 10 0 −10 Phase Phase − ° Gain 100k Gain −20 Gain − V/V VDD = 3.
PAGE 9
DRV593 DRV594 www.ti.com SLOS401C – OCTOBER 2002 – REVISED JULY 2010 DRV593 CLOSED LOOP RESPONSE DRV594 CLOSED LOOP RESPONSE 16 10 4 0 14 Phase −10 12 Gain − V/V −40 Phase − ° −30 2 −10 Phase −20 Gain 0 10 −20 8 −30 6 −40 4 −50 Phase − ° 3 Gain − V/V 10 Gain −50 1 −60 VDD = 3.3 V No Load 0 10 100 2 −70 −80 100k 1k 10k f − Frequency − Hz 0 10 −60 100 1k 10 k −70 100 k f − Frequency − Hz Figure 12. Figure 13.
PAGE 10
DRV593 DRV594 SLOS401C – OCTOBER 2002 – REVISED JULY 2010 www.ti.com INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE 20 10 19 8 VIO − Input Offset Voltage − mV VIO − Input Offset Voltage − mV 9 VDD = 5 V No Load 7 6 5 4 3 2 18 17 16 15 14 13 12 11 1 0 1.2 VDD = 3.3 V No Load 1.6 2.0 2.4 2.8 3.2 VIC − Common-Mode Input Voltage − V 3.6 3.8 10 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 VIC − Common-Mode Input Voltage − V Figure 16. 10 2.
PAGE 11
DRV593 DRV594 www.ti.com SLOS401C – OCTOBER 2002 – REVISED JULY 2010 APPLICATION INFORMATION PULSE-WIDTH MODULATION SCHEME FOR DRV593 AND DRV594 The pulse-width modulation scheme implemented in the DRV593 and DRV594 eliminates one-half of the full output filter previously required for PWM drivers. The DRV593 and DRV594 require only one inductor and capacitor for the output filter. The H/C outputs determine the direction of the current and do not switch back and forth.
PAGE 12
DRV593 DRV594 SLOS401C – OCTOBER 2002 – REVISED JULY 2010 www.ti.com HEATING MODE Figure 19 shows the DRV593 and DRV594 in heating mode. The H/C output is at VDD and the PWM output is proportional to the voltage across the load. The differential voltage across the load is determined using Equation 3. The variables are the same as used previously for Equation 1 and Equation 2. V Load + –(1–D) V DD (3) For example, a 50% duty cycle, shown in Figure 19, results in –2.5 V across the load for VDD = 5 V.
PAGE 13
DRV593 DRV594 www.ti.com SLOS401C – OCTOBER 2002 – REVISED JULY 2010 To avoid this phenomenon, hysteresis should be implemented in the control loop to prevent the device from operating within this region. Although planning for operation during the zero-crossing is important, the normal operating points for the DRV593 and DRV594 are outside of this region.
PAGE 14
DRV593 DRV594 SLOS401C – OCTOBER 2002 – REVISED JULY 2010 www.ti.com OUTPUT FILTER CONSIDERATIONS TEC element manufacturers provide electrical specifications for maximum dc current and maximum output voltage for each particular element. The maximum ripple current, however, is typically only recommended to be less than 10% with no reference to the frequency components of the current.
PAGE 15
DRV593 DRV594 www.ti.com SLOS401C – OCTOBER 2002 – REVISED JULY 2010 For the DRV593 and DRV594, the differential output switching frequency is typically selected to be 500 kHz. The resonant frequency for the filter is typically chosen to be at least one order of magnitude lower than the switching frequency. Equation 5 may then be simplified to give the following magnitude Equation 6. These equations assume the use of the filter in Figure 22.
PAGE 16
DRV593 DRV594 SLOS401C – OCTOBER 2002 – REVISED JULY 2010 www.ti.com For a 100 mF electrolytic capacitor, an ESR of 0.1 Ω is common. If the 10 µH inductor is used, delivering 250 mA of ripple current to the capacitor (as calculated above), then the ripple voltage is 25 mV. This is over ten times that of the 10 mF ceramic capacitor, as ceramic capacitors typically have negligible ESR.
PAGE 17
DRV593 DRV594 www.ti.com SLOS401C – OCTOBER 2002 – REVISED JULY 2010 AREF CAPACITOR The AREF terminal is the output of an internal mid-rail voltage regulator used for the onboard oscillator and ramp generator. The regulator may not be used to provide power to any additional circuitry. A 1 mF ceramic capacitor must be connected from AREF to AGND for stability (see oscillator components above for AGND connection information).
PAGE 18
DRV593 DRV594 SLOS401C – OCTOBER 2002 – REVISED JULY 2010 ǒ T A + TJ * θ JA P DISS www.ti.com Ǔ (12) PRINTED-CIRCUIT BOARD (PCB) LAYOUT CONSIDERATIONS Since the DRV593 and DRV594 are high-current switching devices, a few guidelines for the layout of the printed-circuit board (PCB) must be considered: 1. Grounding.
PAGE 19
DRV593 DRV594 www.ti.com SLOS401C – OCTOBER 2002 – REVISED JULY 2010 Changes from Revision A (October 2002) to Revision B Page • Changed Thermal trip point from 115°C to 128°C ................................................................................................................ 3 • Changed Thermal shtudown point from 128°C to 158°C .....................................................................................................
PAGE 20
PACKAGE OPTION ADDENDUM www.ti.
PAGE 21
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DRV593VFPR HLQFP VFP 32 1000 330.0 16.4 9.6 9.6 1.9 12.0 16.0 Q2 DRV594VFPR HLQFP VFP 32 1000 330.0 16.4 9.6 9.6 1.9 12.0 16.
PAGE 22
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV593VFPR HLQFP VFP 32 1000 367.0 367.0 38.0 DRV594VFPR HLQFP VFP 32 1000 367.0 367.0 38.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.