Datasheet

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DRV603

LEFT

RIGHT

DAC

DRV603

www.ti.com

SLOS617C –JANUARY 2009–REVISED NOVEMBER 2009

DirectPath™, 3-VRMS Line Driver With Adjustable Gain

Check for Samples: DRV603

FEATURES

DESCRIPTION

234

• DirectPath™

The DRV603PW is a 3-V

RMS

pop-free stereo line

driver designed to allow the removal of the output

– Eliminates Pop/Clicks

dc-blocking capacitors for reduced component count

– Eliminates Output DC-Blocking Capacitors

and cost. The device is ideal for single-supply

– Provides Flat Frequency Response 20

electronics where size and cost are critical design

Hz–20 kHz

parameters.

• Low Noise and THD

Designed using TI’s patented DirectPath™

– SNR > 109 dB

technology, The DRV603 is capable of driving 3 V

rms

into a 2.5-kΩ load with 5-V supply voltage. The

– Typical Vn < 7 μVms

device has differential inputs and uses external

– THD+N < 0.002%

gain-setting resistors to support a gain range of ±1

• Output Voltage Into 2.5-kΩ Load

V/V to ±10 V/V, and line outputs that have ±8 kV IEC

ESD protection. The DRV603 (occasionally referred

– 2 Vrms With 3.3-V Supply Voltage

to as the ‘603) has built-in shutdown control for

– 3 Vrms With 5-V Supply Voltage

pop-free on/off control. The DRV603 has an external

• Differential Input

and internal undervoltage detector that mutes the

output.

• External Undervoltage Mute

Using the DRV603 in audio products can reduce

APPLICATIONS

component count considerably compared to

• PDP / LCD TV

traditional methods of generating a 3-V

rms

output. The

DRV603 does not require a power supply greater

• Blu-ray Disc™, DVD Players

than 5 V to generate its 8.5-V

output, nor does it

• Home Theater in a Box

require a split-rail power supply. The DRV603

• Set-Top Boxes

integrates its own charge pump to generate a

negative supply rail that provides a clean, pop-free

ground biased 3-V

rms

output.

The DRV603 is available in a 14-pin TSSOP.

If the low noise and trimmed dc-offset and external

undervoltage mute function are not beneficial in the

application, TI recommends the footprint compatible

DRV602.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2DirectPath is a trademark of Texas Instruments.

3Blu-ray Disc is a trademark of Blu-ray Disc Association.

4All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (21 pages)

PAGE 1
DRV603 www.ti.com SLOS617C – JANUARY 2009 – REVISED NOVEMBER 2009 DirectPath™, 3-VRMS Line Driver With Adjustable Gain Check for Samples: DRV603 FEATURES DESCRIPTION • DirectPath™ – Eliminates Pop/Clicks – Eliminates Output DC-Blocking Capacitors – Provides Flat Frequency Response 20 Hz–20 kHz • Low Noise and THD – SNR > 109 dB – Typical Vn < 7 μVms – THD+N < 0.002% • Output Voltage Into 2.5-kΩ Load – 2 Vrms With 3.
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DRV603 SLOS617C – JANUARY 2009 – REVISED NOVEMBER 2009 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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DRV603 www.ti.com SLOS617C – JANUARY 2009 – REVISED NOVEMBER 2009 ELECTRICAL CHARACTERISTICS TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT |VOS| Output offset voltage VDD = 3 V to 5 V, input grounded, unity gain 1 PSRR Power-supply rejection ratio VDD = 3 V to 5 V mV VOH High-level output voltage VDD = 3.3 V, RL = 2.5 kΩ VOL Low-level output voltage VDD = 3.3 V, RL = 2.5 kΩ –3.
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DRV603 SLOS617C – JANUARY 2009 – REVISED NOVEMBER 2009 www.ti.com PW PACKAGE (TOP VIEW) +INR 1 14 +IN -INR 2 13 -INL OUTR 3 12 OUTL 11 UVP External Under Voltage Detector SGND 4 EN 5 10 PGND PVSS 6 9 PVDD 8 CP CN Charge Pump 7 PIN FUNCTIONS PIN NAME NO.
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DRV603 www.ti.
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DRV603 SLOS617C – JANUARY 2009 – REVISED NOVEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS VDD = 3.3 V , TA = 25°C, RL = 2.5 kΩ, C(PUMP) = C(VSS) = 1 µF , CIN = 10 µF, RIN = 10 kΩ, Rfb = 20 kΩ (unless otherwise noted) TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT VOLTAGE VDD = 3.3 V, RL = 100 kΩ, f = 1 kHz TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT VOLTAGE VDD = 5 V, RL = 100 kΩ, f = 1 kHz 10 THD+N - Total Harmonic Distortion+Noise - % THD+N - Total Harmonic Distortion+Noise - % 10 1 0.1 0.01 0.
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DRV603 www.ti.com SLOS617C – JANUARY 2009 – REVISED NOVEMBER 2009 TYPICAL CHARACTERISTICS (continued) VDD = 3.3 V , TA = 25°C, RL = 2.5 kΩ, C(PUMP) = C(VSS) = 1 µF , CIN = 10 µF, RIN = 10 kΩ, Rfb = 20 kΩ (unless otherwise noted) TOTAL HARMONIC DISTORTION+NOISE vs FREQUENCY VDD = 3.3 V, RL = 2.5 kΩ, VO = 2 Vrms TOTAL HARMONIC DISTORTION+NOISE vs FREQUENCY VDD = 5 V, RL = 100 kΩ, VO = 2 Vrms 10 THD+N - Total Harmonic Distortion+Noise - % THD+N - Total Harmonic Distortion+Noise - % 10 1 0.1 0.01 0.
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DRV603 SLOS617C – JANUARY 2009 – REVISED NOVEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS (continued) VDD = 3.3 V , TA = 25°C, RL = 2.5 kΩ, C(PUMP) = C(VSS) = 1 µF , CIN = 10 µF, RIN = 10 kΩ, Rfb = 20 kΩ (unless otherwise noted) FFT vs FREQUENCY VDD = 5 V, RL = 100 kΩ, VO = 3 Vrms (-60 dB) QUIESCENT CURRENT vs SUPPLY VOLTAGE +0 14m No Load, VI = 0 V -20 Quiescent Current - A 12m FFT - dBr -40 -60 -80 -100 10m 8m 6m 4m -120 2m 0 -0 -140 0 5k 10k 15k 20k f - Frequency - Hz Figure 9.
PAGE 9
DRV603 www.ti.com SLOS617C – JANUARY 2009 – REVISED NOVEMBER 2009 APPLICATION INFORMATION LINE DRIVER AMPLIFIERS Single-supply line-driver amplifiers typically require dc-blocking capacitors. The top drawing in Figure 11 illustrates the conventional line-driver amplifier connection to the load and output signal. DC blocking capacitors are often large in value, and a mute circuit is needed during power up to minimize click and pop.
PAGE 10
DRV603 SLOS617C – JANUARY 2009 – REVISED NOVEMBER 2009 www.ti.com CHARGE PUMP FLYING CAPACITOR AND PVSS CAPACITOR The charge pump flying capacitor serves to transfer charge during the generation of the negative supply voltage. The PVSS capacitor must be at least equal to the charge pump capacitor in order to allow maximum charge transfer. Low-ESR capacitors are an ideal selection, and a value of 1 μF is typical.
PAGE 11
DRV603 www.ti.com SLOS617C – JANUARY 2009 – REVISED NOVEMBER 2009 INPUT-BLOCKING CAPACITORS DC input-blocking capacitors are required to be added in series with the audio signal into the input pins of the DRV603. These capacitors block the dc portion of the audio source and allow the DRV603 inputs to be properly biased to provide maximum performance. These capacitors form a high-pass filter with the input resistor, RIN. The cutoff frequency is calculated using Equation 1.
PAGE 12
DRV603 SLOS617C – JANUARY 2009 – REVISED NOVEMBER 2009 www.ti.com POP-FREE POWER UP Pop-free power up is ensured by keeping the SD (shutdown pin) low during power-supply ramp up and ramp down. The SD pin should be kept low until the input ac-coupling capacitors are fully charged before asserting the SD pin high to achieve pop-less power up. Figure 14 illustrates the preferred sequence. Supply Enable Supply Ramp Time for ac-coupling capacitors to charge Figure 14.
PAGE 13
DRV603 www.ti.com SLOS617C – JANUARY 2009 – REVISED NOVEMBER 2009 APPLICATION CIRCUIT LEFT OUTPUT R12 5 V Supply R11 R2 Linear Low Drop Regulator 10 mF + LEFT INPUT System Supply C3 R1 C3 R1 C2 R3 C1 1mF CP PVDD PGND UVP OUTL Short Circuit Protection C1 DRV603 Line Driver Bias Circuitry CN PVSS -INR OUTR C1 +INR R2 SGND Line Driver Click and Pop Suppression 1mF EN R2 -INL + R3 +INL - + RIGHT INPUT C3 R1 C3 R1 C2 R3 R3 C1 R2 RIGHT OUTPUT 1mF R1 = 5.
PAGE 14
DRV603 SLOS617C – JANUARY 2009 – REVISED NOVEMBER 2009 www.ti.com REVISION HISTORY NOTE: Page numbers of current version may differ from previous versions. Changes from Revision A (February 2009) to Revision B Page • Changed Crosstalk spec from –80dB to –100dB ................................................................................................................. 3 • Added missing voltage value (1.25V) to External Undervoltage Detection threshold equation. ...................................
PAGE 15
DRV603 www.ti.com SLOS617C – JANUARY 2009 – REVISED NOVEMBER 2009 Changes from Revision B (October 2009) to Revision C Page • Changed maximum operating junction temperature ............................................................................................................. 2 • In Dissipation Ratings section, changed θJx to RθJx in three places and 185°C to 185°C/W ............................................... 2 • Corrected reference to Figure 11 ..........................................
PAGE 16
PACKAGE OPTION ADDENDUM www.ti.com 18-Nov-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty DRV603PW ACTIVE TSSOP PW 14 DRV603PWR ACTIVE TSSOP PW 14 90 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
PAGE 17
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device DRV603PWR Package Package Pins Type Drawing TSSOP PW 14 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 12.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) 5.6 1.6 8.0 W Pin1 (mm) Quadrant 12.
PAGE 18
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV603PWR TSSOP PW 14 2000 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.