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User's Guide

SLOU288–February 2010

DRV604PWPEVM

This user's guide describes the operation of the evaluation module for the DRV604. The user’s guide also

provides measurement data and design information like schematic, BOM and PCB layout.

Contents

1 Overview ..................................................................................................................... 2

2 Quick Setup Guide .......................................................................................................... 4

3 On/Off Sequence ............................................................................................................ 4

4 Component Selection ....................................................................................................... 5

5 Layout Recommendations ................................................................................................. 7

6 DRV604PWPEVM Performance .......................................................................................... 7

7 Related Documentation from Texas Instruments ..................................................................... 15

8 Design Documentation .................................................................................................... 16

List of Figures

1 DRV604PWPEVM EVM Photo............................................................................................ 3

2 Power-Up/-Down Sequence ............................................................................................... 4

3 2

Order Active Low-Pass Filter, SE Input .............................................................................. 5

4 THD+N vs Voltage (Line Output) ......................................................................................... 9

5 THD+N vs Power (HeadPhone Output).................................................................................. 9

6 THD+N vs Frequency (Line Output) .................................................................................... 10

DirectPath, FilterPro are trademarks of Texas Instruments.

SLOU288–February 2010 DRV604PWPEVM

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Summary of content (20 pages)

PAGE 1
User's Guide SLOU288 – February 2010 DRV604PWPEVM DRV604PWPEVM This user's guide describes the operation of the evaluation module for the DRV604. The user’s guide also provides measurement data and design information like schematic, BOM and PCB layout. 1 2 3 4 5 6 7 8 Contents Overview ..................................................................................................................... 2 Quick Setup Guide ...................................................................................
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Overview www.ti.com DRV604PWPEVM (continued) 7 THD+N vs Frequency (HeadPhone Output) ........................................................................... 10 8 FFT Spectrum with –60-dBFS Tone (Line Output).................................................................... 11 9 FFT Spectrum with –60-dBFS Tone (Head-Phone Output) 11 10 Channel Separation, Line Output 12 11 12 13 14 15 16 17 18 ......................................................... .......................................
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Overview www.ti.com Table 1.
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Quick Setup Guide 2 www.ti.com Quick Setup Guide This chapter describes the DRV604PWPEVM board in regards to power supply and system interfaces. The chapter provides information regarding handling and unpacking, absolute operating conditions, and a description of the factory default switch and jumper configuration. The following is a step-by-step guide to configuring the DRV604PWPEVM for device evaluation. 2.
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Component Selection www.ti.com 4 Component Selection 4.1 Charge Pump The charge pump flying capacitors, C28 and C29, serves to transfer charge during the generation of the negative supply voltage. The PVSS capacitors, C11 and C13, must be at least equal to the charge pump capacitor in order to allow maximum charge transfer. Low ESR capacitors are an ideal selection, and a value of 1µF is typical.
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Component Selection www.ti.com This topology demands a unity gain stable opamp, if that's not the case, a capacitor from inverting input to GND of the same value as C1 is used. That increases the high frequency gain to 2. The component values can be calculated with the help of the TI FilterPro™ program available on: http://focus.ti.com/docs/toolsw/folders/print/filterpro.html In Table 3 various proposals for the filter and gain settings can be found. Table 3.
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Layout Recommendations www.ti.com The selected thresholds can be determined as follows: (R2 + R3) VUVP = 1.25 V ´ R3 æ R2 ö VHysteresis = 5 μA × R4 ç + 1÷ è R3 ø With the condition R4 >> R2||R3 For example, to obtain VUVP = 4.5V and 400mV hysteresis, we can use R2=10k, R3=3k9 and R4 = 22k. To filter supply spikes and noise a capacitor across R3 can be added.
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DRV604PWPEVM Performance www.ti.com Table 6. Audio Performance Line Output Audio Performance Analog Input Notes/Conditions THD+N, 5 kΩ 0.02 Vrms < 0.070 % 1 kHz (Noise limited) THD+N, 5 kΩ 0.2 Vrms < 0.007 % 1 kHz (Noise limited) THD+N, 5 kΩ 2 Vrms < 0.002 % 1 kHz Dynamic range > 109 dB Ref: 2Vrms, A-weighted, AES17 filter Noise voltage < 7 mVRMS A-weighted, AES17 filter < 1 mV No signal, 2.5-kΩ load > 100 dB 1 kHz, 2 Vrms ±0.5 dB 2 Vrms / 2.
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DRV604PWPEVM Performance www.ti.com 6.1 THD+N vs Voltage and Power THD+N - Total Harmonic Distortion + Noise - % 10 5 Load = 10 kW 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 0.0005 0.0002 0.0001 100m 200m 300m 400m 500m 700m 1 V - Voltage - VRMS 2 3 Blue: 10 kΩ Figure 4. THD+N vs Voltage (Line Output) The THD+N up to over 1Vrms are dominated by noise. 0.001% equals –100dB ! 10 THD+N - Total Harmonic Distortion + Noise - % 5 Load = 32 W In Phase 1 Out of Phase 0.5 0.2 0.1 0.05 0.
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DRV604PWPEVM Performance 6.2 www.ti.com THD+N vs Frequency 10 THD+N - Total Harmonic Distortion + Noise - % 5 Load = 5 kW 1 0.5 0.2 0.1 0.05 200 mVRMS 2 VRMS 0.01 0.005 0.002 0.001 20 50 100 200 500 1k f - Frequency - Hz 2k 5k 10k 20k 10k 20k Green 200mVrms Blue: 2Vrms Load Impedance 5kΩ Figure 6. THD+N vs Frequency (Line Output) 10 THD+N - Total Harmonic Distortion + Noise - % 5 Load = 32 W, AES17 Filter 1 0.5 0.2 0.1 0.05 2 mWRMS 0.01 0.005 20 mWRMS 0.002 0.
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DRV604PWPEVM Performance www.ti.com 6.3 FFT Spectrum with –60dBFS Tone Reference voltage is 2Vrms. FFT size 16k. 0 -20 FFT - dBrA -40 -60 -80 -100 -120 -140 0 5k 10 k f - Frequency - Hz 15 k 20 k Figure 8. FFT Spectrum with –60-dBFS Tone (Line Output) Vertical spacer 0 -20 FFT - dBrA -40 -60 -80 -100 -120 -140 0 5k 10 k f - Frequency - Hz 15 k 20 k Figure 9.
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DRV604PWPEVM Performance 6.4 www.ti.com Channel Separation 10 0 -10 0 dB (2VRMS) -20 -30 dBrA (dB) -40 -50 -60 Right to Left -70 -80 Left to Right -90 -100 -110 20 50 100 200 500 1k f - Frequency - Hz 2k 5k 10k 20k 10k 20k Comments: Green: 0dB (2vrms) Blue: Left to right Red: Right to left Figure 10.
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DRV604PWPEVM Performance www.ti.com 6.5 Frequency Response 10 5 0 dBrA (dB) -5 -10 -15 -20 -25 -30 -35 -4020 50 100 200 500 1k 2k 5k f - Frequency - Hz 10k 20k 50k 200k 1Vrms output, 10kΩ load, 500kHz measurement filter, 2Vrms reference Figure 12.
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DRV604PWPEVM Performance 6.6 www.ti.com Pop/Click (Enable) Shown with and without input signal applied. The measurement results are presented in time domain. Load 5 kΩ. Power supply is applied, and then the shutdown signal is released. The enable signal is used to trigger the measuring system. Enable Output = 100 mV/div Zero Input Signal Enable Output = 2 V/div 1 V Input Signal, 2 V Output Figure 13. Pop/Click (Enable) 6.7 Pop/Click (Disable) Shown with and without input signal applied.
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Related Documentation from Texas Instruments www.ti.com 7 Related Documentation from Texas Instruments Table 9 contains a list of data manuals that have detailed descriptions of the integrated circuits used in the design of the DRV604PWPEVM. The data manuals can be obtained at the URL http://www.ti.com. Table 9.
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J1 2 1 GND +5V INHP_L INHP_R DRV604PWPEVM Copyright © 2010, Texas Instruments Incorporated C6 10ufd/16V KGA GND + RCA (Red) RCA(Black) HP IN C1 3 2 SOT223-DCY 3.3V 800mA TLV1117-33 GND 1 VIN VOUT GND VR1 4.7 DNP 0603 C8 GND 0.1ufd/16V 0603 C2 10ufd/16V KGA GND + +3.3V 3 1 2 3 1 10 0603 R28 10 0603 R14 C19 100K 0603 RCA (Red) RCA(Black) 100K 0603 R15 R23 R1 INLD_L INLD_R 2 100K 0603 GND GND LINE IN R6 10 0603 R27 10 0603 R13 100K 0603 R5 1.
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Design Documentation www.ti.com 8.2 Parts List Table 10. Bill of Materials MANU Part No. QTY Ref Des Vendor Part No. Description Vendor MANU TI-SEMICONDUCTORS DRV604PWP 1 U1 DRV604PWP NEED DATA, TSSOP28-PWP ROHS TI TI TLV1117-33CDCYR 1 VR1 296-21112-1 VOLT REG LDO 3.
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Design Documentation 8.3 www.ti.com PCB Layers Gerber files are available on the EVM page for download Figure 16. DRV604PWPEVM PCB Component Placement Figure 17. DRV604PWPEVM PCB Top Layer Figure 18.
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EVALUATION BOARD/KIT IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have electronics training and observe good engineering practice standards.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.