Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - motor controllers Pre-driver - half bridge (3) Parallel HTSSOP 56

PVDD

GH_A

GH_B

GH_C

Motor

Controller

Three-Phase

NMOS Gate

Driver

GL_A

GL_B

GL_C

offset

Buck

Converter

MOTOR

DRV8302

offset

ADC1

ADC2

PWM

Control

and

Protection

Logic

Error

Reporting

3 or 6

Vref

Control

DRV8302

www.ti.com

SLES267 –AUGUST 2011

Three Phase Pre-Driver with Dual Current Shunt Amplifiers and Buck Regulator –

Hardware Controlled

Check for Samples: DRV8302

FEATURES

DESCRIPTION

The DRV8302 is a gate driver IC for three phase

• Operating Supply Voltage 8V–60V

motor drive applications. It provides three half bridge

• 2.3A Sink and 1.7A Source Gate Drive Current

drivers, each capable of driving two N-type

Capability

MOSFETs, one for the high-side and one for the low

• Integrated Dual Shunt Current Amplifiers With

side. It supports up to 2.3A sink and 1.7A source

peak current capability and only needs a single power

Adjustable Gain and Offset

supply with a wide range from 8 to 60V. The

• Integrated Buck Converter to Support up to

DRV8302 uses bootstrap gate drivers with trickle

1.5A External Load

charge circuitry to support 100% duty cycle. The gate

• Independent Control of 3 or 6 PWM Inputs

driver uses automatic hand shaking when high side

FET or low side FET is switching to prevent current

• Bootstrap Gate Driver With 100% Duty Cycle

shoot through. Vds of FETs is sensed to protect

Support

external power stage during overcurrent conditions.

• Programmable Dead Time to Protect External

The DRV8302 includes two current shunt amplifiers

FETs from Shoot Through

for accurate current measurement. The current

• Programmable Overcurrent Protection of

amplifiers support bi-directional current sensing and

External MOSFETs

provide an adjustable output offset of up to 3V.

• Thermally Enhanced 56-Pin TSSOP Pad Down

The DRV8302 also has an integrated switching mode

DCA Package

buck converter with adjustable output and switching

frequency to support MCU or additional system power

APPLICATIONS

needs. The buck is capable to drive up to 1.5A load.

• 3-Phase Brushless DC Motor and Permanent

Magnet Synchronous Motor

• CPAP and Pump

• E-bike, Hospital Bed, Wheel Chair

• Power Drill, Blender, Chopper

Figure 1. DRV8302 Simplified Application Schematic

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (21 pages)

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DRV8302 SLES267 – AUGUST 2011 www.ti.com Three Phase Pre-Driver with Dual Current Shunt Amplifiers and Buck Regulator – Hardware Controlled Check for Samples: DRV8302 FEATURES DESCRIPTION • • The DRV8302 is a gate driver IC for three phase motor drive applications. It provides three half bridge drivers, each capable of driving two N-type MOSFETs, one for the high-side and one for the low side. It supports up to 2.3A sink and 1.
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DRV8302 SLES267 – AUGUST 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DEVICE INFORMATION PIN ASSIGNMENT The DRV8302 is designed to fit the 56pin DCA package. Here is the pinout of the device.
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DRV8302 SLES267 – AUGUST 2011 www.ti.com PIN FUNCTIONS PIN NAME NO. I/O (1) DESCRIPTION RT_CLK 1 I Resistor timing and external clock for buck regulator. Resistor should connect to GND (power pad) with very short trace to reduce the potential clock jitter due to noise. COMP 2 O Buck error amplifier output and input to the output switch current comparator. VSENSE 3 I Buck output voltage sense pin. Inverting node of error amplifier.
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DRV8302 SLES267 – AUGUST 2011 www.ti.com PIN FUNCTIONS (continued) PIN I/O (1) DESCRIPTION NAME NO. SL_C 34 I Low-Side MOSFET source connection, half-bridge C. Low-side VDS measured between this pin and SH_C. GL_C 35 O Gate drive output for Low-Side MOSFET, half-bridge C SH_C 36 I High-Side MOSFET source connection, half-bridge C. High-side VDS measured between this pin and PVDD1.
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DRV8302 SLES267 – AUGUST 2011 www.ti.
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DRV8302 SLES267 – AUGUST 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) VALUE MIN MAX –0.3 70 UNITS PVDD Supply voltage range including transient Relative to PGND PVDDRAMP Maximum supply voltage ramp rate Voltage rising up to PVDDMAX VPGND Maximum voltage between PGND and GND ±0.
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DRV8302 SLES267 – AUGUST 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS PVDD1 DC supply voltage PVDD1 for normal operation Relative to PGND PVDD2 DC supply voltage PVDD2 for buck converter CAVDD External capacitance on AVDD pin (ceramic cap) 20% tolerance CDVDD CGVDD MIN TYP MAX 8 60 3.5 60 UNITS V V 1 µF External capacitance on DVDD pin (ceramic cap) 20% tolerance 1 µF External capacitance on GVDD pin (ceramic cap) 20% tolerance 2.
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DRV8302 SLES267 – AUGUST 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) PVDD = 8-60 V, TC = 25°C, unless specified under test condition PARAMETER TEST CONDITIONS MIN TYP MAX UNIT GATE DRIVE OUTPUT: GH_A, GH_B, GH_C, GL_A, GL_B, GL_C VGX_NORM Gate driver Vgs voltage PVDD = 8–60V Ioso1 Maximum source current setting 1, peak Vgs of FET equals to 2 V. REG 0x02 9.5 1.7 11.5 A Iosi1 Maximum sink current setting 1, peak Vgs of FET equals to 8 V. REG 0x02 2.
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DRV8302 SLES267 – AUGUST 2011 www.ti.
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DRV8302 SLES267 – AUGUST 2011 www.ti.com CURRENT SHUNT AMPLIFIER CHARACTERISTICS TC = 25°C unless otherwise specified PARAMETER TEST CONDITIONS MIN TYP MAX UNIT G1 Gain option 1 (GAIN = 0V) 9.5 10 10.5 V/V G2 Gain Option 2 (GAIN = 2V) 38 40 42 V/V Tsettling Settling time to 1% Tc = 0-60°C, G = 10, Vstep = 2 V 300 ns Tsettling Settling time to 1% Tc = 0-60°C, G = 40, Vstep = 2 V 1.2 µs Vswing Output swing linear range 0.3 Slew Rate 5.
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DRV8302 SLES267 – AUGUST 2011 www.ti.com FUNCTIONAL DESCRIPTION THREE-PHASE GATE DRIVER The DRV8302 provides three half bridge drivers, each capable of driving two N-type MOSFETs, one for the high-side and one for the low side. Gate driver has following features: • Internal hand shake between high side and low side FETs during switching transition to prevent current shoot through.
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DRV8302 SLES267 – AUGUST 2011 www.ti.com DC_CAL SN 200 kW S2 50 kW S1 5 kW AVDD _ 100 W DC_CAL SO 5 kW + SP 50 kW S1 200 kW S2 DC_CAL Vref /2 REF _ AVDD 50 kW + 50 kW Figure 2. Current Shunt Amplifier Simplified Block Diagram BUCK CONVERTER Although integrated in the same device, buck converter is designed completely independent of rest of the gate driver circuitry.
PAGE 13
DRV8302 SLES267 – AUGUST 2011 www.ti.com The buck has a power good comparator (PWRGD) which asserts when the regulated output voltage is less than 92% or greater than 109% of the nominal output voltage. The PWRGD pin is an open drain output which deasserts when the VSENSE pin voltage is between 94% and 107% of the nominal output voltage allowing the pin to transition high when a pull-up resistor is used.
PAGE 14
DRV8302 SLES267 – AUGUST 2011 www.ti.com R1 + R2 ≥ 100 KΩ DVDD = 3.3 V Connect OC_ADJ pin to DVDD to disable the over-current protection feature. DVDD R1 VOC OC_ADJ R2 Figure 3. OC_ADJ Current Programming Pin Connection Under-Voltage Protection (UVP) To protect the power output stage during startup, shutdown and other possible under-voltage conditions, the DRV8302 provides power stage under-voltage protection by driving its outputs low whenever PVDD is below 6V (PVDD_UV) or GVDD is below 8V (GVDD_UV).
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DRV8302 SLES267 – AUGUST 2011 www.ti.com Table 1.
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DRV8302 SLES267 – AUGUST 2011 www.ti.com PIN CONTROL FUNCTIONS EN_GATE EN_GATE low is used to put gate driver, charge pump, current shunt amplifier, and internal regulator blocks into a low power consumption mode to save energy. Device will put the MOSFET output stage to high impedance mode as long as PVDD is still present.
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DRV8302 SLES267 – AUGUST 2011 www.ti.com APPLICATION SCHEMATIC EXAMPLE Example: Buck: PVDD= 3.5V – 40V, Iout_max = 1.5A, Vo = 3.3V, Fs = 570 kHz VCC 120 pF PVDD 0 .015 mF 6.8 nF 205 kW 3 .3 16 .2 KW SS_TR RT _CLK 31.6 kW EN_BUCK COMP 10 kW 10kW 10kW VCC 10 nF VSENSE PVDD 2 PWRGD PVDD 2 PVDD 0.1 mF 0.1 mF 10 kW OCTW BST _BK FAULT PH DTC PH 2.2 mF M_OC BST _A GAIN GH_A OC_ADJ SH_A DC_CAL GL_A GVDD 22 nF CP1 Motor Controller CP2 PWM EN_GATE ADC 1 mF 4.
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PACKAGE OPTION ADDENDUM www.ti.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.