Datasheet

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Not Recommended for New Designs

DRV8402

www.ti.com

SLES222 –FEBRUARY 2009

Dual Full Bridge PWM Motor Driver

Check for Samples: DRV8402

The DRV8402 can operate at up to 500 kHz

FEATURES

switching frequency while still maintaining precise

• High-Efficiency Power Stage (up to 96%) with

control and high efficiency. It also has an innovative

Low R

DS(on)

MOSFETs (80 mΩ at T

= 25°C)

protection system integrated on-chip, safeguarding

• Operating Supply Voltage up to 50 V

the device against a wide range of fault conditions

that could damage the system. These safeguards are

(65 V Absolute Maximum)

short-circuit protection, overcurrent protection,

• 10 A Continuous Output Current and 24 A

undervoltage protection, and two-stage thermal

Peak Current per Device

protection. The DRV8402 has a current-limiting circuit

• PWM Operating Frequency up to 500 kHz

that prevents device shutdown during load transients

such as motor start-up. A programmable overcurrent

• Integrated Self-Protection Circuits

detector allows adjustable current limit and protection

• Programmable Cycle-by-Cycle Current Limit

level to meet different motor requirements.

Protection

The DRV8402 has unique independent supply and

• Independent Supply and Ground Pins for Each

ground pins for each half bridge, which makes it

Half Bridge

possible to provide current measurement through

• Intelligent Gate Drive and Cross Conduction

external shunt resistor and support multiple motors

Prevention

with different power supply voltage requirements.

• No External Snubber or Schottky Diode is

Simplified Application Diagram

Required

• Thermally Enhanced DKD (36-pin PSOP3)

Package

APPLICATIONS

• Brushed DC, Brushless DC, and Stepper

Motors

• Three Phase Permanent Magnet Synchronous

Motors

• Robotic and Haptic Control System

• Actuators and Pumps

• Precision Instruments

• TEC Drivers

DESCRIPTION

The DRV8402 is a high performance, integrated dual

full bridge motor driver with an advanced protection

system. Because of the low R

DS(on)

and intelligent

gate drive design, the efficiency of this motor driver

can be up to 96%, which enables the use of smaller

power supplies and heatsinks, and is a good

candidate for energy efficient applications. This

device requires two power supplies, one at 12V for

GVDD and VDD, and one up to 50V for PVDD. The

DRV8402 is capable of driving 5 A continuous RMS

current and 12 A peak current per full bridge with low

idle power dissipation. It can also be used for up to

10 A continuous current and 24 A peak current in

parallel full bridge operation.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (20 pages)

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Not Recommended for New Designs DRV8402 SLES222 – FEBRUARY 2009 www.ti.
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Not Recommended for New Designs DRV8402 SLES222 – FEBRUARY 2009 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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Not Recommended for New Designs DRV8402 SLES222 – FEBRUARY 2009 www.ti.com DEVICE INFORMATION Pin Assignment The DRV8402 is available in a thermally enhanced package: • 36-pin PSOP3 package (DKD) This package contains a heat slug that is located on the top side of the device for convenient thermal coupling to the heatsink.
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Not Recommended for New Designs DRV8402 SLES222 – FEBRUARY 2009 www.ti.com Pin Functions PIN (1) DESCRIPTION DKD NO.
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Not Recommended for New Designs DRV8402 SLES222 – FEBRUARY 2009 www.ti.com SYSTEM BLOCK DIAGRAM VDD 4 Undervoltage Protection OTW Internal Pullup Resistors to VREG FAULT M1 Protection and I/O Logic M2 M3 4 VREG VREG Power On Reset AGND Temp. Sense GND RESET_AB Overload Protection RESET_CD Isense OC_ADJ GVDD_D BST_D PVDD_D PWM_D PWM Rcv. Ctrl. Timing Gate Drive OUT_D FB/PFB−Configuration Pulldown Resistor GND_D GVDD_C BST_C PVDD_C PWM_C PWM Rcv. Ctrl.
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Not Recommended for New Designs DRV8402 SLES222 – FEBRUARY 2009 www.ti.com ELECTRICAL CHARACTERISTICS Ta = 25 °C, PVDD = 50 V, GVDD = VDD = 12 V, FSw = 400 kHz, unless otherwise noted. All performance is in accordance with recommended operating conditions unless otherwise specified.
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Not Recommended for New Designs DRV8402 SLES222 – FEBRUARY 2009 www.ti.com TYPICAL CHARACTERISTICS EFFICIENCY vs SWITCHING FREQUENCY NORMALIZED RDS(on) vs GATE DRIVE, GVDD 1.10 100 TJ = 25°C Normalized RDS(on) / (RDS(on) at 12 V) 90 80 Efficiency – % 70 60 50 40 30 Full Bridge 20 Load = 5 A PVDD = 50 V TC = 75°C 10 0 0 50 1.08 1.06 1.04 1.02 1.00 0.98 0.96 8.0 100 150 200 250 300 350 400 450 500 8.5 9.0 10.0 10.5 11.0 11.
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Not Recommended for New Designs DRV8402 SLES222 – FEBRUARY 2009 www.ti.com TYPICAL CHARACTERISTICS (continued) OUTPUT DUTY CYCLE vs INPUT DUTY CYCLE 100 fS = 500 kHz TC = 25°C 90 Output Duty Cycle – % 80 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 80 90 100 Input Duty Cycle – % Figure 5.
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Not Recommended for New Designs DRV8402 SLES222 – FEBRUARY 2009 www.ti.com THEORY OF OPERATION POWER SUPPLIES To help with system design, the DRV8402 needs only a 12 V supply in addition to power-stage supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog circuitry.
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Not Recommended for New Designs DRV8402 SLES222 – FEBRUARY 2009 www.ti.com ERROR REPORTING Bootstrap Capacitor Under Voltage Protection The FAULT and OTW pins are both active-low, open-drain outputs. Their function is for protection-mode signaling to a PWM controller or other system-control device. When the device runs at a low switching frequency (e.g.
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Not Recommended for New Designs DRV8402 SLES222 – FEBRUARY 2009 www.ti.com For added flexibility, the OC threshold is programmable within a limited range using a single external resistor connected between the OC_ADJ pin and AGND pin. See Table 2 for information on the correlation between programming-resistor value and the OC threshold. It should be noted that a properly functioning overcurrent detector assumes the presence of a proper inductor at the power-stage output (minimum 2 μH).
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Not Recommended for New Designs DRV8402 SLES222 – FEBRUARY 2009 www.ti.com DIFFERENT MODE OPERATIONS The DRV8402 supports three operations: 1. Full bridge (FB) mode 2. Parallel full bridge (PFB) mode 3. Half bridge (HB) mode different mode In full bridge and half bridge modes, PWM_A controls half bridge A, PWM_B controls both half bridge B, etc. Figure 6 shows an application example for full bridge mode operation.
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Not Recommended for New Designs DRV8402 SLES222 – FEBRUARY 2009 www.ti.com RθJA is a system thermal resistance from junction to ambient air.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device DRV8402DKDR Package Package Pins Type Drawing SPQ HSSOP 500 DKD 36 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 24.4 Pack Materials-Page 1 14.7 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 16.4 4.0 20.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV8402DKDR HSSOP DKD 36 500 367.0 367.0 45.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.