Datasheet

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DRV8800

DRV8801

www.ti.com

SLVS855G –JULY 2008–REVISED OCTOBER 2013

DMOS FULL-BRIDGE MOTOR DRIVERS

Check for Samples: DRV8800, DRV8801

FEATURES

• Low ON-Resistance [R

ds(ON)

] Outputs

• Crossover-Current Protection

• Overcurrent Protection • 16-Pin QFN With PowerPAD™ Package

• Motor Lead Short-to-Supply Protection

APPLICATIONS

• Short-to-Ground Protection

• Printers

• Low-Power Mode

• Industrial Automation

• Synchronous Rectification

• Diagnostic Output

• Internal Undervoltage Lockout (UVLO)

DESCRIPTION/ORDERING INFORMATION

Designed to control dc motors by using pulse width modulation (PWM), the DRV8800/DRV8801 is capable of

peak output currents up to ±2.8 A and operating voltages up to 36 V.

The PHASE and ENABLE inputs provide dc motor speed and direction control by applying external pulse-width

modulation (PWM) and control signals. Internal synchronous rectification control circuitry provides lower power

dissipation during PWM operation.

Internal circuit protection includes motor lead short-to-supply/short-to-ground, thermal shutdown with hysteresis,

undervoltage monitoring of VBB and VCP, and crossover-current protection.

The DRV8800/DRV8801 is supplied in a thin-profile 16-pin QFN (RTY) PowerPAD™ package, providing

enhanced thermal dissipation. The devices are lead free (Pb free).

ORDERING INFORMATION

PACKAGE

(1) (2)

ORDERABLE PART NUMBER TOP-SIDE MARKING

DRV8800RTYR DRV8800

DRV8800RTYT DRV8800

Plastic QFN 16 (S-PQFP-16) – RTY

DRV8801RTYR DRV8801

DRV8801RTYT DRV8801

–40°C to 85°C

DRV8800PWP DRV8800

DRV8800PWPR DRV8800

TSSOP - PWP

DRV8801PWP DRV8801

DRV8801PWPR DRV8801

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (27 pages)

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DRV8800 DRV8801 www.ti.
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DRV8800 DRV8801 SLVS855G – JULY 2008 – REVISED OCTOBER 2013 www.ti.com DRV8801 RTY PACKAGE (TOP VIEW) nFAULT VPROPI VCP 14 13 VCP 13 15 VREG 14 MODE 1 nFAULT 15 16 MODE 16 DRV8800 RTY PACKAGE (TOP VIEW) nSLEEP 3 10 CP1 nSLEEP 3 10 CP1 ENABLE 4 9 OUT- ENABLE 4 9 OUT- 8 CP2 VBB 11 7 2 SENSE GND 6 CP2 OUT+ 11 5 2 MODE 2 GND 8 GND VBB 12 7 1 SENSE PHASE 6 GND OUT+ 12 5 1 NC PHASE NC – Do not connect TERMINAL FUNCTIONS TERMINAL NO.
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DRV8800 DRV8801 www.ti.com SLVS855G – JULY 2008 – REVISED OCTOBER 2013 DRV8800 PWP PACKAGE (TOP VIEW) DRV8801 PWP PACKAGE (TOP VIEW) nFAULT 1 16 NC MODE 2 15 VREG PHASE 3 14 VCP GND 4 13 GND nSLEEP 5 12 CP2 ENABLE 6 11 CP1 OUT+ 7 10 OUT- SENSE 8 9 VBB nFAULT 1 16 MODE 2 MODE 1 2 15 VPROPI PHASE 3 14 VCP GND 4 13 GND nSLEEP 5 12 CP2 ENABLE 6 11 CP1 OUT+ 7 10 OUT- SENSE 8 9 VBB NC – Do not connect TERMINAL FUNCTIONS TERMINAL NO.
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DRV8800 DRV8801 SLVS855G – JULY 2008 – REVISED OCTOBER 2013 www.ti.com Figure 1.
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DRV8800 DRV8801 www.ti.com SLVS855G – JULY 2008 – REVISED OCTOBER 2013 Figure 2.
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DRV8800 DRV8801 SLVS855G – JULY 2008 – REVISED OCTOBER 2013 www.ti.com Figure 3. DRV8800 FUNCTIONAL BLOCK DIAGRAM .1 uf CP1 CP2 VBB VCP .1 uf Charge Pump VREG Optional VBB Low-Side Gate Supply .22 uf Bias Supply MODE 100 uf PHASE .1 uf OUT+ M ENABLE VDD Control Logic OUT- 3.3K 3.
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DRV8800 DRV8801 www.ti.com SLVS855G – JULY 2008 – REVISED OCTOBER 2013 Figure 4. DRV8801 FUNCTIONAL BLOCK DIAGRAM .1 uf CP1 VPROPI X5 CP2 VBB VCP SENSE .1 uf Charge Pump VBB MODE 1 Bias Supply MODE 2 PHASE 100 uf .1 uf OUT+ M Control Logic ENABLE VDD OUT3.3K 3.
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DRV8800 DRV8801 SLVS855G – JULY 2008 – REVISED OCTOBER 2013 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN VBB Load supply voltage VSense MAX (2) 40 Output current 2.8 Sense voltage ±500 VBB to OUTx OUTx to SENSE Logic input voltage (2) VDD ESD rating –0.
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DRV8800 DRV8801 www.ti.com SLVS855G – JULY 2008 – REVISED OCTOBER 2013 ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN fPWM < 50 kHz IBB Motor supply current TYP 6 Charge pump on, Outputs disabled VIL VIH VIL IIH IIL IIH IIL IIH IIL 0.8 2.7 nSLEEP input voltage 0.8 VIN = 2 V PHASE, MODE input current <1.0 20 ≤–2.0 20 VIN = 2 V 40 100 VIN = 0.8 V 16 40 VIN = 2.7 V 27 50 VIN = 0.8 V <1 10 VIN = 0.
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DRV8800 DRV8801 SLVS855G – JULY 2008 – REVISED OCTOBER 2013 www.ti.com SLEEP ENABLE PHASE MODE VBB VOUT+ 0 VBB VOUT- 0 IOUTX 0 A 1 2 3 4 5 6 7 VIN 1 8 9 VIN 5 6 7 OUT+ OUT- 3 2 OUT+ OUT- 4 8 9 A Charge Pump and VREG power on delay (~200 us) Figure 5.
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DRV8800 DRV8801 www.ti.com SLVS855G – JULY 2008 – REVISED OCTOBER 2013 VOUT+ VOUT- High-Z IPEAK IOUTx IOCP Enable, Source or Sink BLANK Charge Pump Counter tBLANK tOCP NFAULT Motor Lead Short Condition Normal DC Motor Capacitance Figure 6. Overcurrent Control Timing FUNCTIONAL DESCRIPTION Device Operation The DRV8800/DRV8801 is designed to drive one dc motor. The current through the output full-bridge switches and all N-channel DMOS are regulated with a fixed off-time PWM control circuit.
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DRV8800 DRV8801 SLVS855G – JULY 2008 – REVISED OCTOBER 2013 www.ti.com Charge Pump The charge pump is used to generate a supply above VBB to drive the source-side DMOS gates. A 0.1-μF ceramic monolithic capacitor should be connected between CP1 and CP2 for pumping purposes. A 0.1-μF ceramic monolithic capacitor, CStorage, should be connected between VCP and VBB to act as a reservoir to run the high-side DMOS devices.
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DRV8800 DRV8801 www.ti.
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DRV8800 DRV8801 SLVS855G – JULY 2008 – REVISED OCTOBER 2013 www.ti.com APPLICATION INFORMATION Power Dissipation First-order approximation of power dissipation in the DRV8800/DRV8801 can be calculated by examining the power dissipation in the full-bridge during each of the operation modes. DRV8800/DRV8801 utilize synchronous rectification. During the decay cycle, the body diode is shorted by the low-Rds(ON) driver, which in turn reduces power dissipation in the full-bridge.
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DRV8800 DRV8801 www.ti.com SLVS855G – JULY 2008 – REVISED OCTOBER 2013 DRV8801 VBB 4 1 3 2 1 Drive Current 2 Fast decay with synchronous rectification (reverse) 3 Slow decay with synchronous rectification (brake) Low Side 4 Slow decay with synchronous rectification (brake) High Side Figure 7. Current Path Fast Decay With Synchronous Rectification This decay mode is equivalent to a phase change where the opposite drivers are switched on.
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DRV8800 DRV8801 SLVS855G – JULY 2008 – REVISED OCTOBER 2013 www.ti.com Slow-Decay SR (Brake Mode) In slow-decay mode, both low-side sinking drivers turn on, allowing the current to circulate through the H-bridge’s low side (two sink drivers) and the load. Power dissipation I2R loses in the two sink DMOS drivers: 2 PD = I (2 ´ RDS(on)Sink) (2) SENSE A low-value resistor can be placed between the SENSE pin and ground for current-sensing purposes.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com (4) 14-Oct-2013 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device DRV8800PWPR Package Package Pins Type Drawing SPQ HTSSOP 2000 330.0 12.4 PWP 16 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.9 5.6 1.6 8.0 12.0 Q1 DRV8800RTYT QFN RTY 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 DRV8801PWPR HTSSOP PWP 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV8800PWPR HTSSOP PWP 16 2000 367.0 367.0 35.0 DRV8800RTYT QFN RTY 16 250 210.0 185.0 35.0 DRV8801PWPR HTSSOP PWP 16 2000 367.0 367.0 35.0 DRV8801RTYT QFN RTY 16 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.