Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - buffer amplifiers LVDS 1.5 GBit/s WQFN 48

Mux Buffer

Switch

Fabric A

Switch

Fabric B

FPGA

ASIC

Backplane or Cable

LVDS

DS15MB200

www.ti.com

SNLS196E –NOVEMBER 2005–REVISED MARCH 2013

DS15MB200 Dual 1.5 Gbps 2:1/1:2 LVDS Mux/Buffer with Pre-Emphasis

Check for Samples: DS15MB200

FEATURES

DESCRIPTION

The DS15MB200 is a dual-port 2 to 1 multiplexer and

• 1.5 Gbps Data Rate Per Channel

1 to 2 repeater/buffer. High-speed data paths and

• Configurable Off/On Pre-emphasis Drives

flow-through pinout minimize internal device jitter and

Lossy Backplanes and Cables

simplify board layout, while pre-emphasis overcomes

• LVDS/BLVDS/CML/LVPECL Compatible Inputs,

ISI jitter effects from lossy backplanes and cables.

The differential inputs and outputs interface to LVDS

LVDS Compatible Outputs

or Bus LVDS signals such as those on Texas

• Low Output Skew and Jitter

Instrument's 10-, 16-, and 18-bit Bus LVDS SerDes,

• On-chip 100Ω Input and Output Termination

or to CML or LVPECL signals.

• 15 kV ESD Protection on LVDS Inputs/Outputs

The 3.3V supply, CMOS process, and robust I/O

• Hot Plug Protection

ensure high performance at low power over the entire

industrial -40 to +85°C temperature range.

• Single 3.3V Supply

• Industrial -40 to +85°C Temperature Range

• 48-pin WQFN Package

Typical Application

Figure 1.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (18 pages)

PAGE 1
DS15MB200 www.ti.com SNLS196E – NOVEMBER 2005 – REVISED MARCH 2013 DS15MB200 Dual 1.5 Gbps 2:1/1:2 LVDS Mux/Buffer with Pre-Emphasis Check for Samples: DS15MB200 FEATURES DESCRIPTION • • The DS15MB200 is a dual-port 2 to 1 multiplexer and 1 to 2 repeater/buffer. High-speed data paths and flow-through pinout minimize internal device jitter and simplify board layout, while pre-emphasis overcomes ISI jitter effects from lossy backplanes and cables.
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DS15MB200 SNLS196E – NOVEMBER 2005 – REVISED MARCH 2013 www.ti.com Block Diagram PREA_0 ENA_0 PREB_0 ENB_0 SOA_0 LI_0 SOB_0 PREL_0 ENL_0 SIA_0 LO_0 SIB_0 MUX_S0 Channel 0 Channel 1 Figure 2. PIN DESCRIPTIONS Pin Name WQFN Pin Number I/O, Type Description SWITCH SIDE DIFFERENTIAL INPUTS SIA_0+ SIA_0− 30 29 I, LVDS Switch A-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or LVPECL compatible.
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DS15MB200 www.ti.com SNLS196E – NOVEMBER 2005 – REVISED MARCH 2013 PIN DESCRIPTIONS (continued) Pin Name WQFN Pin Number I/O, Type Description DIGITAL CONTROL INTERFACE MUX_S0 MUX_S1 38 11 I, LVTTL Mux Select Control Inputs (per channel) to select which Switch-side input, A or B, is passed through to the Line-side. PREA_0 PREA_1 PREB_0 PREB_1 26 23 25 24 I, LVTTL Output pre-emphasis control for Switch-side outputs.
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DS15MB200 SNLS196E – NOVEMBER 2005 – REVISED MARCH 2013 www.ti.com Output Characteristics The output characteristics of the DS15MB200 have been optimized for point-to-point backplane and cable applications, and are not intended for multipoint or multidrop signaling.
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DS15MB200 www.ti.com SNLS196E – NOVEMBER 2005 – REVISED MARCH 2013 Absolute Maximum Ratings (1) Value Unit Supply Voltage (VDD) −0.3 to +4.0 V CMOS Input Voltage -0.3 to (VDD+0.3) V -0.3 to (VDD+0.3) V LVDS Receiver Input Voltage (2) LVDS Driver Output Voltage -0.3 to (VDD+0.3) V +40 mA Junction Temperature +150 °C Storage Temperature −65 to +150 °C Lead Temperature (Solder, 4sec) 260 °C Max Pkg Power Capacity @ 25°C 5.2 W Thermal Resistance (θJA) 24 °C/W 41.
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DS15MB200 SNLS196E – NOVEMBER 2005 – REVISED MARCH 2013 www.ti.com Electrical Characteristics Over recommended operating supply and temperature ranges unless other specified. Symbol Parameter Conditions Min Typ (1) Max Units V LVTTL DC SPECIFICATIONS (MUX_Sn, PREA_n, PREB_n, PREL_n, ENA_n, ENB_n, ENL_n) VIH High Level Input Voltage 2.0 VDD VIL Low Level Input Voltage GND 0.
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DS15MB200 www.ti.com SNLS196E – NOVEMBER 2005 – REVISED MARCH 2013 Electrical Characteristics (continued) Over recommended operating supply and temperature ranges unless other specified. Symbol tJIT Parameter Jitter (0% Pre-emphasis) Conditions (5) RJ - Alternating 1 and 0 at 750MHz Min (6) Typ (1) Max Units 1.1 1.5 psrms DJ - K28.5 Pattern, 1.5 Gbps (7) 20 34 psp-p TJ - PRBS 27-1 Pattern, 1.
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DS15MB200 SNLS196E – NOVEMBER 2005 – REVISED MARCH 2013 www.ti.com WQFN Performance Characteristics Power Supply Current vs. Bit Data Rate 300 250 200 Total Jitter vs. Bit Data Rate 60 50 PRE-EMPHASIS ON TOTAL JITTER (ps) POWER SUPPLY CURRENT (mA) 350 PRE-EMPHASIS OFF 150 100 40 30 VCM = 1.2V 20 VCM = 0.25V 10 50 VCM = 3.
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DS15MB200 www.ti.com SNLS196E – NOVEMBER 2005 – REVISED MARCH 2013 TRI-STATE AND POWERDOWN MODES The DS15MB200 has output enable control on each of the six onboard LVDS output drivers. This control allows each output individually to be placed in a low power TRI-STATE mode while the device remains active, and is useful to reduce power consumption on unused channels. In TRI-STATE mode, some outputs may remain active while some are in TRI-STATE.
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DS15MB200 SNLS196E – NOVEMBER 2005 – REVISED MARCH 2013 www.ti.com 0.1 PF 50: 15MB200 LVPECL 50: R1 150: 0.1 PF R2 150: Figure 9. AC Coupled LVPECL to LVDS Interface An AC coupled interface is preferred when transmitter and receiver ground references differ more than 1 V. This is a likely scenario when transmitter and receiver devices are on separate PCBs. Figure 9 illustrates an AC coupled interface between a LVPECL driver and LVDS receiver.
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DS15MB200 www.ti.com SNLS196E – NOVEMBER 2005 – REVISED MARCH 2013 VDD 0.1 PF R1 83: R2 83: 50: LVPECL 15MB200 50: 0.1 PF R3 130: R4 130: Figure 11. AC Coupled LVDS to LVPECL Interface Figure 11 illustrates AC coupled interface between an LVDS driver and LVPECL receiver without a VT pin available. The resistors R1, R2, R3, and R4, if not present in the receiver (2), provide a load for the driver, terminate the transmission line, and bias the signal for the receiver.
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DS15MB200 SNLS196E – NOVEMBER 2005 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision D (March 2013) to Revision E • 12 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing DS15MB200TSQ WQFN RHS 48 DS15MB200TSQ/NOPB WQFN RHS DS15MB200TSQX/NOPB WQFN RHS SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 48 2500 330.0 16.4 7.3 7.3 1.3 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS15MB200TSQ WQFN RHS 48 250 213.0 191.0 55.0 DS15MB200TSQ/NOPB WQFN RHS 48 250 213.0 191.0 55.0 DS15MB200TSQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.
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MECHANICAL DATA RHS0048A SQA48A (Rev B) www.ti.
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