Datasheet

PEEQ
V
CC
ASIC / FPGA
PE EQ
V
CC
CML
LVDS
LVPECL
ASIC / FPGA
LVDS
BR100
BR100
DS25BR100
www.ti.com SNLS217F –MARCH 2007–REVISED APRIL 2013
DS25BR100 / DS25BR101 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and
Receive Equalization
Check for Samples: DS25BR100
1
FEATURES
DESCRIPTION
The DS25BR100 and DS25BR101 are single channel
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• DC - 3.125 Gbps Low Jitter, High Noise
3.125 Gbps LVDS buffers optimized for high-speed
Immunity, Low Power Operation
signal transmission over lossy FR-4 printed circuit
• Receive Equalization Reduces ISI Jitter Due to
board backplanes and balanced metallic cables. Fully
Media Loss
differential signal paths ensure exceptional signal
integrity and noise immunity.
• Transmit Pre-Emphasis Drives Lossy
Backplanes and Cables
The DS25BR100 and DS25BR101 feature transmit
• On-Chip 100Ω Input and Output Termination:
pre-emphasis (PE) and receive equalization (EQ),
making them ideal for use as a repeater device.
– Minimizes Insertion and Return Losses
Other LVDS devices with similar IO characteristics
– Reduces Component Count
include the following products. The DS25BR120
– Minimizes Board Space
features four levels of pre-emphasis for use as an
optimized driver device, while the DS25BR110
• DS25BR101 Eliminates On-Chip Input
features four levels of equalization for use as an
Termination for Added Design Flexibility
optimized receiver device. The DS25BR150 is a
• 7 kV ESD on LVDS I/O Pins Protects Adjoining
buffer/repeater with the lowest power consumption
Components
and does not feature transmit pre-emphasis nor
• Small 3 mm x 3 mm WSON-8 Space Saving
receive equalization.
Package
Wide input common mode range allows the receiver
to accept signals with LVDS, CML and LVPECL
APPLICATIONS
levels; the output levels are LVDS. A very small
package footprint requires minimal space on the
• Clock and Data Buffering
board while the flow-through pinout allows easy board
• Metallic Cable Driving and Equalization
layout. On the DS25BR100 the differential input and
• FR-4 Equalization
output is internally terminated with a 100Ω resistor to
lower return losses, reduce component count and
further minimize board space. For added design
flexibility the 100Ω input terminations on the
DS25BR101 have been eliminated. This elimination
enables a designer to adjust the termination for
custom interconnect topologies and layout.
Typical Application
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PRODUCTION DATA information is current as of publication date.
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Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
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