Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - buffer amplifiers, repeaters LVDS 3.125 GBit/s WSON 8

ASIC / FPGA

CML

LVDS

LVPECL

ASIC / FPGA

LVDS

BR110

DS25BR110

www.ti.com

SNLS255E –MARCH 2007–REVISED APRIL 2013

DS25BR110 3.125 Gbps LVDS Buffer with Receive Equalization

Check for Samples: DS25BR110

FEATURES

DESCRIPTION

The DS25BR110 is a single channel 3.125 Gbps

• DC - 3.125 Gbps Low Jitter, High Noise

LVDS buffer optimized for high-speed signal

Immunity, Low Power Operation

transmission over lossy FR-4 printed circuit board

• Four Levels of Receive Equalization Reduce

backplanes and balanced metallic cables. A fully

ISI Jitter

differential signal path ensures exceptional signal

integrity and noise immunity.

• On-Chip 100Ω Input and Output Termination

Minimizes Insertion and Return Losses,

The DS25BR110 features four levels of receive

Reduces Component Count, and Minimizes

equalization (EQ), making it ideal for use as a

Board Space

receiver device. Other LVDS devices with similar IO

characteristics include the following products. The

• 7 kV ESD on LVDS I/O Pins Protects Adjoining

DS25BR120 features four levels of pre-emphasis for

Components

use as an optimized driver device, while the

• Small 3 mm x 3 mm 8-WSON Space Saving

DS25BR100 features both pre-emphasis and

Package

equalization for use as an optimized repeater device.

The DS25BR150 is a buffer/repeater with the lowest

APPLICATIONS

power consumption and does not feature transmit

pre-emphasis nor receive equalization.

• Clock and Data Buffering

• Metallic Cable Equalization Wide input common mode range allows the receiver

to accept signals with LVDS, CML and LVPECL

• FR-4 Equalization

levels; the output levels are LVDS. A very small

package footprint requires minimal space on the

board while the flow-through pinout allows easy board

layout. The differential inputs and outputs are

internally terminated with a 100Ω resistor to lower

device input and output return losses, reduce

component count, and further minimize board space.

Typical Application

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (18 pages)

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DS25BR110 www.ti.com SNLS255E – MARCH 2007 – REVISED APRIL 2013 DS25BR110 3.125 Gbps LVDS Buffer with Receive Equalization Check for Samples: DS25BR110 FEATURES DESCRIPTION • The DS25BR110 is a single channel 3.125 Gbps LVDS buffer optimized for high-speed signal transmission over lossy FR-4 printed circuit board backplanes and balanced metallic cables. A fully differential signal path ensures exceptional signal integrity and noise immunity. 1 2 • • • • DC - 3.
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DS25BR110 SNLS255E – MARCH 2007 – REVISED APRIL 2013 www.ti.com Block Diagram EQ0 EQ1 IN+ OUT+ IN- OUT- Pin Diagram EQ0 1 IN+ 2 IN- 3 EQ1 4 8 VCC DAP 7 OUT+ GND 6 OUT- 5 NC Pin Descriptions Pin Name Type Number Description EQ0 1 Input Equalizer select pin. IN+ 2 Input Non-inverting LVDS input pin. IN- 3 Input Inverting LVDS input pin. EQ1 4 Input Equalizer select pin. NC 5 NA "NO CONNECT" pin. OUT- 6 Output Inverting LVDS output pin.
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DS25BR110 www.ti.com SNLS255E – MARCH 2007 – REVISED APRIL 2013 Absolute Maximum Ratings (1) (2) −0.3V to +4V Supply Voltage (VCC) −0.3V to (VCC + 0.3V) LVCMOS Input Voltage (EQ0, EQ1) LVDS Input Voltage (IN+, IN−) −0.3V to +4V Differential Input Voltage |VID| 1.0V −0.3V to (VCC + 0.3V) LVDS Output Voltage (OUT+, OUT−) LVDS Differential Output Voltage ((OUT+) - (OUT−)) 0V to 1.
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DS25BR110 SNLS255E – MARCH 2007 – REVISED APRIL 2013 www.ti.com DC Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) (3) Parameter Test Conditions Min Typ Max Units V LVCMOS INPUT DC SPECIFICATIONS (EQ0, EQ1) VIH High Level Input Voltage 2.0 VCC VIL Low Level Input Voltage GND 0.8 V IIH High Level Input Current VIN = 3.6V VCC = 3.6V 0 ±10 μA IIL Low Level Input Current VIN = GND VCC = 3.
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DS25BR110 www.ti.com SNLS255E – MARCH 2007 – REVISED APRIL 2013 AC Electrical Characteristics (1) Over recommended operating supply and temperature ranges unless otherwise specified.
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DS25BR110 SNLS255E – MARCH 2007 – REVISED APRIL 2013 www.ti.com AC Electrical Characteristics(1) (continued) Over recommended operating supply and temperature ranges unless otherwise specified.(2)(3) Parameter tTJ1C tTJ2C Total Jitter (Peak to Peak) Test Channel E (8) Test Conditions VID = 350 mV VCM = 1.2V PRBS-23 (NRZ) EQ0 = 0, EQ1 = 1 Min Typ Max Units 2.5 Gbps 0.07 0.12 UIP-P 3.125 Gbps 0.12 0.
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DS25BR110 www.ti.com SNLS255E – MARCH 2007 – REVISED APRIL 2013 DC TEST CIRCUITS VOH OUT+ IN+ Power Supply R D RL Power Supply IN- OUTVOL Figure 1. Differential Driver DC Test Circuit AC Test Circuits and Timing Diagrams OUT+ IN+ R Signal Generator D IN- RL OUT- Figure 2. Differential Driver AC Test Circuit Figure 3. Propagation Delay Timing Diagram Figure 4.
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DS25BR110 SNLS255E – MARCH 2007 – REVISED APRIL 2013 www.ti.com 50: Microstrip 50: Microstrip L = A, B or C L=1" L=1" L=1" 50: Microstrip L=1" 100: Differential Stripline 50: Microstrip Figure 6. Test Channel Description Test Channel Loss Characteristics The test channel was fabricated with Polyclad PCL-FR-370-Laminate/PCL-FRP-370 Prepreg materials (Dielectric constant of 3.7 and Loss Tangent of 0.02).
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DS25BR110 www.ti.com SNLS255E – MARCH 2007 – REVISED APRIL 2013 CML3.3V or CML2.5V VCC 50: 100: Differential T-Line 50: OUT+ IN+ DS25BR110 IN- OUT- Figure 8. Typical CML Driver DC-Coupled Interface to DS25BR110 Input LVPECL Driver OUT+ 100: Differential T-Line LVDS Receiver IN+ 100: OUT150-250: IN150-250: Figure 9. Typical LVPECL Driver DC-Coupled Interface to DS25BR110 Input OUTPUT INTERFACING The DS25BR110 outputs signals compliant to the LVDS standard.
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DS25BR110 SNLS255E – MARCH 2007 – REVISED APRIL 2013 www.ti.com Typical Performance 4.50 4.50 w/ EQ TA = 25°C NRZ PRBS-7 TJ = 0.25 UI 3.75 3.00 MAXIMUM DATA RATE (Gbps) MAXIMUM DATA RATE (Gbps) VCC = 3.3V 2.25 w/ EQ 1.50 0.75 w/o EQ 3.75 3.00 2.25 1.50 TA = 25°C NRZ PRBS-7 TJ = 0.5 UI 0.75 0 0 0 3 6 9 12 15 0 3 CAT5e LENGTH (m) 6 9 12 15 CAT5e LENGTH (m) Figure 11. Maximum Data Rate as a Function of CAT5e (Belden 1700A) Length Figure 12.
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DS25BR110 www.ti.com SNLS255E – MARCH 2007 – REVISED APRIL 2013 Typical Performance (continued) Figure 17. A 2.5 Gbps NRZ PRBS-7 After 70" Differential FR-4 Stripline V:100 mV / DIV, H:75 ps / DIV Figure 18. An Equalized 2.5 Gbps NRZ PRBS-7 After 70" Differential FR-4 Stripline V:100 mV / DIV, H:75 ps / DIV Figure 19. A 3.125 Gbps NRZ PRBS-7 After 70" Differential FR-4 Stripline V:100 mV / DIV, H:50 ps / DIV Figure 20. An Equalized 3.
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DS25BR110 SNLS255E – MARCH 2007 – REVISED APRIL 2013 www.ti.com Typical Performance (continued) 150 150 70" FR4 Stripline 125 TA = 25°C NRZ PRBS-7 EQ = Medium 40" FR4 Stripline 100 75 30" FR4 Stripline 50 20" FR4 Stripline 25 TOTAL RESIDUAL JITTER (ps) TOTAL RESIDUAL JITTER (ps) VCC = 3.3V VCC = 3.3V TA = 25°C NRZ PRBS-7 EQ = High 125 100 60" FR4 Stripline 75 50 40" FR4 Stripline 25 50" FR4 Stripline 0 0 0.8 1.6 2.4 3.2 0 4.0 0 0.8 DATA RATE (Gbps) Figure 23.
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DS25BR110 www.ti.com SNLS255E – MARCH 2007 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision D (April 2013) to Revision E • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DS25BR110TSD/NOPB WSON NGQ 8 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 DS25BR110TSDX/NOPB WSON NGQ 8 4500 330.0 12.4 3.3 3.3 1.0 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS25BR110TSD/NOPB WSON NGQ 8 1000 213.0 191.0 55.0 DS25BR110TSDX/NOPB WSON NGQ 8 4500 367.0 367.0 35.
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MECHANICAL DATA NGQ0008A SDA08A (Rev A) www.ti.
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