Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - buffer amplifiers, repeaters LVDS 3.125 GBit/s WSON 8

ASIC / FPGA

CML

LVDS

LVPECL

ASIC / FPGA

LVDS

BR120

DS25BR120

www.ti.com

SNLS256E –MARCH 2007–REVISED APRIL 2013

DS25BR120 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis

Check for Samples: DS25BR120

FEATURES

DESCRIPTION

The DS25BR120 is a single channel 3.125 Gbps

• DC - 3.125 Gbps Low Jitter, High Noise

LVDS buffer optimized for high-speed signal

Immunity, Low Power Operation

transmission over lossy FR-4 printed circuit board

• Four Levels of Transmit Pre-Emphasis Drive

backplanes and balanced metallic cables. Fully

Lossy Backplanes and Cables

differential signal paths ensure exceptional signal

integrity and noise immunity.

• On-Chip 100Ω Input and Output Termination

Minimizes Insertion and Return Losses,

The DS25BR120 features four levels of pre-emphasis

Reduces Component Count, and Minimizes

(PE) for use as an optimized driver device. Other

Board Space

LVDS devices with similar IO characteristics include

the following products. The DS25BR110 features four

• 7 kV ESD on LVDS I/O pins Protects Adjoining

levels of equalization for use as an optimized receiver

Components

device, while the DS25BR100 features both pre-

• Small 3 mm x 3 mm 8-WSON Space Saving

emphasis and equalization for use as an optimized

Package

repeater device. The DS25BR150 is a buffer/repeater

with the lowest power consumption and does not

APPLICATIONS

feature transmit pre-emphasis nor receive

equalization.

• Clock and Data Buffering

• Metallic Cable Driving Wide input common mode range allows the receiver

to accept signals with LVDS, CML and LVPECL

• FR-4 Driving

levels; the output levels are LVDS. A very small

package footprint requires minimal space on the

board while the flow-through pinout allows easy board

layout. The differential inputs and outputs are

internally terminated with a 100Ω resistor to lower

device input and output return losses, reduce

component count and further minimize board space.

Typical Application

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (16 pages)

PAGE 1
DS25BR120 www.ti.com SNLS256E – MARCH 2007 – REVISED APRIL 2013 DS25BR120 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis Check for Samples: DS25BR120 FEATURES DESCRIPTION • The DS25BR120 is a single channel 3.125 LVDS buffer optimized for high-speed transmission over lossy FR-4 printed circuit backplanes and balanced metallic cables. differential signal paths ensure exceptional integrity and noise immunity. 1 2 • • • • DC - 3.
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DS25BR120 SNLS256E – MARCH 2007 – REVISED APRIL 2013 www.ti.com Block Diagram PE0 PE1 IN+ OUT+ IN- OUT- Pin Diagram PE1 1 IN+ 2 IN- 3 PE0 4 8 VCC DAP 7 OUT+ GND 6 OUT- 5 NC WSON Package PIN DESCRIPTIONS Pin Name Pin Name Pin Type Pin Description PE1 1 Input Pre-emphasis select pin. IN+ 2 Input Non-inverting LVDS input pin. IN- 3 Input Inverting LVDS input pin. PE0 4 Input Pre-emphasis select pin. NC 5 NA "NO CONNECT" pin.
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DS25BR120 www.ti.com SNLS256E – MARCH 2007 – REVISED APRIL 2013 Absolute Maximum Ratings (1) (2) −0.3V to +4V Supply Voltage (VCC) −0.3V to (VCC + 0.3V) LVCMOS Input Voltage (PE0, PE1) LVDS Input Voltage (IN+, IN−) −0.3V to +4V Differential Input Voltage |VID| 1.0V −0.3V to (VCC + 0.3V) LVDS Output Voltage (OUT+, OUT−) LVDS Differential Output Voltage ((OUT+) - (OUT−)) 0V to 1.
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DS25BR120 SNLS256E – MARCH 2007 – REVISED APRIL 2013 www.ti.com Electrical Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3) Symbol VCL Parameter Conditions Min ICL = −18 mA, VCC = 0V Input Clamp Voltage Typ Max Units -0.9 −1.5 V 350 450 mV 35 mV 1.
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DS25BR120 www.ti.com SNLS256E – MARCH 2007 – REVISED APRIL 2013 AC Electrical Characteristics(1) (continued) Over recommended operating supply and temperature ranges unless otherwise specified.(2)(3) Symbol Parameter Conditions Min Typ Max Units JITTER PERFORMANCE WITH PE = OFF tRJ1A tRJ2A VID = 350 mV VCM = 1.2V Clock (RZ) PE0 = 0, PE1 = 0 2.5 Gbps 0.5 1 ps 3.125 Gbps 0.5 1 ps VID = 350 mV VCM = 1.2V K28.5 (NRZ) PE0 = 0, PE1 = 0 2.
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DS25BR120 SNLS256E – MARCH 2007 – REVISED APRIL 2013 www.ti.com APPLICATION INFORMATION DC TEST CIRCUITS VOH OUT+ IN+ Power Supply R D RL Power Supply IN- OUTVOL Figure 1. Differential Driver DC Test Circuit AC TEST CIRCUITS AND TIMING DIAGRAMS OUT+ IN+ R Signal Generator D IN- RL OUT- Figure 2. Differential Driver AC Test Circuit Figure 3. Propagation Delay Timing Diagram Figure 4.
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DS25BR120 www.ti.com SNLS256E – MARCH 2007 – REVISED APRIL 2013 50: MS 50: MS L = A, B or C L=1" L=1" L=1" 50: MS L=1" 100: Diff. Stripline 50: MS Figure 6. Test Channel Description Test Channel Loss Characteristics The test channel was fabricated with Polyclad PCL-FR-370-Laminate/PCL-FRP-370 Prepreg materials (Dielectric constant of 3.7 and Loss Tangent of 0.02).
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DS25BR120 SNLS256E – MARCH 2007 – REVISED APRIL 2013 www.ti.com CML3.3V or CML2.5V VCC 50: 100: Differential T-Line 50: OUT+ IN+ DS25BR120 IN- OUT- Figure 8. Typical CML Driver DC-Coupled Interface to DS25BR120 Input LVPECL Driver OUT+ 100: Differential T-Line LVDS Receiver IN+ 100: OUT150-250: IN150-250: Figure 9. Typical LVPECL Driver DC-Coupled Interface to DS25BR120 Input OUTPUT INTERFACING The DS25BR120 outputs signals compliant to the LVDS standard.
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DS25BR120 www.ti.com SNLS256E – MARCH 2007 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS 4.50 4.50 VCC = 3.3V 3.75 MAXIMUM DATA RATE (Gbps) MAXIMUM DATA RATE (Gbps) w/ PE and/or EQ w/ PE 3.00 2.25 w/o PE 1.50 VCC = 3.3V TA = 25°C NRZ PRBS-7 TJ = 0.25 UI 0.75 3.00 2.25 1.50 0 3 6 9 12 w/o PE and EQ 0.75 0 0 15 0 6 CAT5e LENGTH (m) MAXIMUM DATA RATE (Gbps) SUPPLY CURRENT (mA) PE = Low 35 PE = Off 30 VCC = 3.3V 3.75 3.00 2.25 w/o PE 1.50 VCC = 3.
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DS25BR120 SNLS256E – MARCH 2007 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) 10 Figure 16. A 2.5 Gbps NRZ PRBS-7 After 40" Differential FR-4 Stripline V:125 mV / DIV, H:75 ps / DIV Figure 17. A 3.125 Gbps NRZ PRBS-7 After 40" Differential FR-4 Stripline V:125 mV / DIV, H:50 ps / DIV Figure 18. An Equalized (with PE) 2.5 Gbps NRZ PRBS-7 After 40" Differential FR-4 Stripline V:125 mV / DIV, H:75 ps / DIV Figure 19. An Equalized (with PE) 3.
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DS25BR120 www.ti.com SNLS256E – MARCH 2007 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision D (April 2013) to Revision E • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DS25BR120TSD/NOPB WSON NGQ 8 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 DS25BR120TSDX/NOPB WSON NGQ 8 4500 330.0 12.4 3.3 3.3 1.0 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS25BR120TSD/NOPB WSON NGQ 8 1000 213.0 191.0 55.0 DS25BR120TSDX/NOPB WSON NGQ 8 4500 367.0 367.0 35.
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MECHANICAL DATA NGQ0008A SDA08A (Rev A) www.ti.
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