Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - buffer amplifiers, repeaters LVDS 3.125 GBit/s LLP 40 EP

FPGA or ASIC

LVDS I/O

Cable or Backplane

FPGA or ASIC

LVDS I/O

DS25BR440

www.ti.com

SNLS258B –FEBRUARY 2008–REVISED MARCH 2013

DS25BR440 3.125 Gbps Quad LVDS Buffer with Transmit Pre-Emphasis and Receive

Equalization

Check for Samples: DS25BR440

FEATURES

DESCRIPTION

The DS25BR440 is a 3.125 Gbps Quad LVDS buffer

• DC - 3.125 Gbps Low Jitter, Low Skew, Low

optimized for high-speed signal routing and repeating

Power Operation

over lossy FR-4 printed circuit board backplanes and

• Pin Selectable Transmit Pre-Emphasis and

balanced cables. Fully differential signal paths ensure

Receive Equalization Eliminate Data

exceptional signal integrity and noise immunity.

Dependant Jitter

The DS25BR440 features two levels of transmit pre-

• Wide Input Common Mode Voltage Range

emphasis (PE) and two levels of receive equalization

Allows DC-Coupled Interface to LVDS, CML

(EQ). Both of these features compensate for

and LVPECL Drivers

interconnect losses and ultimately maximize noise

margin. A loss-of-signal (LOS) circuit monitors each

• LOS Circuitry Detects Open Inputs Fault

input channel and a unique LOS pin is asserted when

• Integrated 100Ω Input and Output

no signal is detected at that input.

Terminations

Wide input common mode range allows the switch to

• 8 kV ESD on LVDS I/O Pins Protects Adjoining

accept signals with LVDS, CML and LVPECL levels;

Components

the output levels are LVDS. A very small package

• Small 6 mm x 6 mm WQFN-40 Space Saving

footprint requires a minimal space on the board while

Package

the flow-through pinout allows easy board layout.

Each differential input and output is internally

APPLICATIONS

terminated with a 100Ω resistor to lower device return

losses, reduce component count and further minimize

• Clock and Data Buffering and Repeating

board space.

• Copper Cable Driving and Equalization

• FR-4 Equalization

• OC-48 / STM-16

Typical Application

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (18 pages)

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DS25BR440 www.ti.com SNLS258B – FEBRUARY 2008 – REVISED MARCH 2013 DS25BR440 3.125 Gbps Quad LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization Check for Samples: DS25BR440 FEATURES DESCRIPTION • The DS25BR440 is a 3.125 Gbps Quad LVDS buffer optimized for high-speed signal routing and repeating over lossy FR-4 printed circuit board backplanes and balanced cables. Fully differential signal paths ensure exceptional signal integrity and noise immunity. 1 2 • • • • • • DC - 3.
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DS25BR440 SNLS258B – FEBRUARY 2008 – REVISED MARCH 2013 www.ti.
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DS25BR440 www.ti.com SNLS258B – FEBRUARY 2008 – REVISED MARCH 2013 PIN DESCRIPTIONS Pin Name Pin Number IN0+, IN0- , IN1+, IN1-, IN2+, IN2-, IN3+, IN3- I/O, Type Pin Description 1, 2, 4, 5, 6, 7, 9, 10 I, LVDS Inverting and non-inverting high speed LVDS input pins. OUT0+, OUT0-, OUT1+, OUT1-, OUT2+, OUT2-, OUT3+, OUT3- 29, 27, 24, 22, O, LVDS Inverting and non-inverting high speed LVDS output pins. EQ0, EQ1, EQ2, EQ3 40, 39, 11, 12 I, LVCMOS Receive equalization level select pins.
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DS25BR440 SNLS258B – FEBRUARY 2008 – REVISED MARCH 2013 www.ti.com Absolute Maximum Ratings (1) (2) −0.3V to +4V Supply Voltage LVCMOS Input Voltage −0.3V to (VCC + 0.3V) LVCMOS Output Voltage −0.3V to (VCC + 0.3V) −0.3V to +4V LVDS Input Voltage Differential Input Voltage |VID| 1V −0.3V to (VCC + 0.3V) LVDS Output Voltage LVDS Differential Output Voltage 0.
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DS25BR440 www.ti.com SNLS258B – FEBRUARY 2008 – REVISED MARCH 2013 Electrical Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) (3) Symbol Parameter Conditions Min Typ Max Units 0 ±10 μA IIL Low Level Input Current VIN = GND VCC = 3.6V VCL Input Clamp Voltage ICL = −18 mA, VCC = 0V −0.9 −1.5 V VOL Low Level Output Voltage IOL= 4 mA 0.26 0.
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DS25BR440 SNLS258B – FEBRUARY 2008 – REVISED MARCH 2013 www.ti.com AC Electrical Characteristics (1) (2) (continued) Over recommended operating supply and temperature ranges unless otherwise specified.
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DS25BR440 www.ti.com SNLS258B – FEBRUARY 2008 – REVISED MARCH 2013 AC Electrical Characteristics (1) (2) (continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol tDJ1BD tDJ2BD Parameter tTJ2BD Min Typ Max Units Deterministic Jitter (Peak to Peak) Input Test Channel D Output Test Channel B VID = 350 mV VCM = 1.2V K28.5 (NRZ) 2.5 Gbps 11 23 ps 3.
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DS25BR440 SNLS258B – FEBRUARY 2008 – REVISED MARCH 2013 www.ti.com DC TEST CIRCUITS ¼ DS25BR440 Power Supply VOH OUT+ IN+ R D RL Power Supply IN- OUTVOL Figure 1. Differential Driver DC Test Circuit AC Test Circuits and Timing Diagrams ¼ DS25BR440 OUT+ IN+ R Signal Generator D RL IN- OUT- Figure 2. Differential Driver AC Test Circuit Figure 3. Propagation Delay Timing Diagram Figure 4.
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DS25BR440 www.ti.com SNLS258B – FEBRUARY 2008 – REVISED MARCH 2013 DS25BR440 CHARACTERIZATION BOARD TEST CHANNEL ¼ DS25BR440 50: MS 50: MS L=4" L=4" PATTERN GENERATOR OSCILLOSCOPE L=4" L=4" 50: MS 50: MS Figure 6. Pre-emphasis Performance Test Circuit TEST CHANNEL DS25BR440 CHARACTERIZATION BOARD ¼ DS25BR440 50: MS 50: MS L=4" L=4" PATTERN GENERATOR OSCILLOSCOPE L=4" L=4" 50: MS 50: MS Figure 7.
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DS25BR440 SNLS258B – FEBRUARY 2008 – REVISED MARCH 2013 Test Channel Length (inches) www.ti.com Insertion Loss (dB) 500 MHz 750 MHz 1000 MHz 1250 MHz 1500 MHz 1560 MHz A 10 -1.2 -1.7 -2.0 -2.4 -2.7 -2.8 B 20 -2.6 -3.5 -4.1 -4.8 -5.5 -5.6 C 30 -4.3 -5.7 -7.0 -8.2 -9.4 -9.7 D 15 -1.6 -2.2 -2.7 -3.2 -3.7 -3.8 E 30 -3.4 -4.5 -5.6 -6.6 -7.7 -7.9 F 60 -7.8 -10.3 -12.4 -14.5 -16.6 -17.0 Functional Description The DS25BR440 is a 3.
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DS25BR440 www.ti.com SNLS258B – FEBRUARY 2008 – REVISED MARCH 2013 CML3.3V or CML2.5V Driver VCC 50: DS25BR440 Receiver 100: Differential T-Line 50: OUT+ IN+ 100: IN- OUT- Figure 11. Typical CML Driver DC-Coupled Interface to an DS25BR440 Input LVPECL Driver OUT+ 100: Differential T-Line LVDS Receiver IN+ 100: OUT150-250: IN150-250: Figure 12. Typical LVPECL Driver DC-Coupled Interface to an DS25BR440 Input Output Interfacing The DS25BR440 outputs signals compliant to the LVDS standard.
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DS25BR440 SNLS258B – FEBRUARY 2008 – REVISED MARCH 2013 www.ti.com Typical Performance 60 150 VCC = 3.3V TA = 25°C NRZ PRBS-7 EQ = Off PE = Off 40 30 20 100 20" FR4 Stripline 75 50 10 25 0 0 0 0.8 TA = 25°C NRZ PRBS7 EQ = On 125 RESIDUAL JITTER (ps) 50 TOTAL JITTER (ps) VCC = 3.3V 1.6 2.4 3.2 10" FR4 Stripline 0 4.0 0.8 DATA RATE (Gbps) 2.4 3.2 4.0 DATA RATE (Gbps) Figure 14. Total Jitter as a Function of Data Rate Figure 15.
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DS25BR440 www.ti.com SNLS258B – FEBRUARY 2008 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision A (March 2013) to Revision B • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DS25BR440TSQ/NOPB WQFN RTA 40 250 178.0 16.4 6.3 6.3 1.5 12.0 16.0 Q1 DS25BR440TSQX/NOPB WQFN RTA 40 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS25BR440TSQ/NOPB WQFN RTA DS25BR440TSQX/NOPB WQFN RTA 40 250 213.0 191.0 55.0 40 2500 367.0 367.0 38.
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MECHANICAL DATA RTA0040A SQA40A (Rev B) www.ti.
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