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DS25CP102

www.ti.com

SNLS262E –OCTOBER 2007–REVISED MARCH 2013

DS25CP102 3.125 Gbps 2X2 LVDS Crosspoint Switch with Transmit Pre-Emphasis and

Receive Equalization

Check for Samples: DS25CP102

FEATURES

APPLICATIONS

• DC - 3.125 Gbps Low Jitter, Low Skew, Low

• High-Speed Channel Select Applications

Power Operation

• Clock and Data Buffering and Muxing

• Pin Configurable, Fully Differential, Non-

• OC-48 / STM-16

Blocking Architecture

• SD/HD/3GHD SDI Routers

• Pin Selectable Transmit Pre-Emphasis and

Receive Equalization Eliminate Data

DESCRIPTION

Dependant Jitter

The DS25CP102 is a 3.125 Gbps 2x2 LVDS

• Wide Input Common Mode Voltage Range

crosspoint switch optimized for high-speed signal

routing and switching over lossy FR-4 printed circuit

Allows DC-Coupled Interface to CML and

board backplanes and balanced cables. Fully

LVPECL Drivers

differential signal paths ensure exceptional signal

• On-Chip 100Ω Input and Output Termination

integrity and noise immunity. The non-blocking

Minimizes Insertion and Return Losses,

architecture allows connections of any input to any

Reduces Component Count, Minimizes Board

output or outputs.

Space

The DS25CP102 features two levels (Off and On) of

• 8 kV ESD on LVDS I/O Pins Protects Adjoining

transmit pre-emphasis (PE) and two levels (Off and

Components

On) of receive equalization (EQ).

• Small 4 mm x 4 mm WQFN-16 Space Saving

Wide input common mode range allows the switch to

Package

accept signals with LVDS, CML and LVPECL levels;

the output levels are LVDS. A very small package

footprint requires a minimal space on the board while

the flow-through pinout allows easy board layout.

Each differential input and output is internally

terminated with a 100Ω resistor to lower device

insertion and return losses, reduce component count

and further minimize board space.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (20 pages)

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DS25CP102 www.ti.com SNLS262E – OCTOBER 2007 – REVISED MARCH 2013 DS25CP102 3.125 Gbps 2X2 LVDS Crosspoint Switch with Transmit Pre-Emphasis and Receive Equalization Check for Samples: DS25CP102 FEATURES APPLICATIONS • • • • • 1 2 • • • • • • DC - 3.
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DS25CP102 SNLS262E – OCTOBER 2007 – REVISED MARCH 2013 www.ti.
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DS25CP102 www.ti.com SNLS262E – OCTOBER 2007 – REVISED MARCH 2013 PIN DESCRIPTIONS Pin Name Pin Number I/O, Type Pin Description IN0+, IN0- , IN1+, IN1- 1, 2, 3, 4 I, LVDS Inverting and non-inverting high speed LVDS input pins. OUT0+, OUT0-, OUT1+, OUT1- 12, 11, 10, 9 O, LVDS Inverting and non-inverting high speed LVDS output pins. SEL0, SEL1 7, 8 I, LVCMOS Switch configuration pins. There is a 20k pulldown resistor on this pin. EN0, EN1 14, 13 I, LVCMOS Output enable pins.
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DS25CP102 SNLS262E – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com Recommended Operating Conditions Supply Voltage (VCC) Receiver Differential Input Voltage (VID) Min Typ Max Units 3.0 3.3 3.6 V 0 −40 Operating Free Air Temperature (TA) +25 1 V +85 °C DC Electrical Characteristics (1) (2) (3) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units V LVCMOS DC SPECIFICATIONS VIH High Level Input Voltage 2.
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DS25CP102 www.ti.com SNLS262E – OCTOBER 2007 – REVISED MARCH 2013 AC Electrical Characteristics (1) Over recommended operating supply and temperature ranges unless otherwise specified.
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DS25CP102 SNLS262E – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com AC Electrical Characteristics (1) (continued) Over recommended operating supply and temperature ranges unless otherwise specified. (2) (3) Symbol tTJ1D tTJ2D Parameter Conditions Total Jitter (Peak to Peak) Test Channel D VID = 350 mV VCM = 1.2V PRBS-23 (NRZ) (9) Min Typ Max Units 2.5 Gbps 0.07 0.11 UIP-P 3.125 Gbps 0.07 0.
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DS25CP102 www.ti.com SNLS262E – OCTOBER 2007 – REVISED MARCH 2013 Figure 4. LVDS Output Transition Times Pre-Emphasis and Equalization Test Circuits DS25CP102 CHARACTERIZATION BOARD 50: Microstrip 50: Microstrip ½ DS25CP102 L=4" L=4" PATTERN GENERATOR OSCILLOSCOPE L=4" L=4" 50: Microstrip 50: Microstrip Figure 5.
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DS25CP102 SNLS262E – OCTOBER 2007 – REVISED MARCH 2013 TEST CHANNEL www.ti.com DS25CP102 CHARACTERIZATION BOARD 50: Microstrip TEST CHANNEL 50: Microstrip ½ DS25CP102 L=4" L=4" PATTERN GENERATOR OSCILLOSCOPE L=4" L=4" 50: Microstrip 50: Microstrip Figure 8. Pre-Emphasis and Equalization Performance Test Circuit 50: MS 50: MS L = A, B or C L=1" L=1" L=1" 50: MS L=1" 100: Diff. Stripline 50: MS Figure 9.
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DS25CP102 www.ti.com SNLS262E – OCTOBER 2007 – REVISED MARCH 2013 Functional Description The DS25CP102 is a 3.125 Gbps 2x2 LVDS digital crosspoint switch optimized for high-speed signal routing and switching over lossy FR-4 printed circuit board backplanes and balanced cables. Table 1. Switch Configuration Truth Table SEL1 SEL0 OUT1 OUT0 0 0 IN0 IN0 0 1 IN0 IN1 1 0 IN1 IN0 1 1 IN1 IN1 Table 2.
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DS25CP102 SNLS262E – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com CML3.3V or CML2.5V Driver VCC 50: DS25CP102 Receiver 100: Differential T-Line 50: OUT+ IN+ 100: IN- OUT- Figure 11. Typical CML Driver DC-Coupled Interface to DS25CP102 Input LVPECL Driver OUT+ 100: Differential T-Line LVDS Receiver IN+ 100: OUT150-250: IN150-250: Figure 12. Typical LVPECL Driver DC-Coupled Interface to DS25CP102 Input Output Interfacing The DS25CP102 outputs signals that are compliant to the LVDS standard.
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DS25CP102 www.ti.com SNLS262E – OCTOBER 2007 – REVISED MARCH 2013 Typical Performance Characteristics 60 60 VCC = 3.3V 40 50 TOTAL JITTER (ps) TOTAL JITTER (ps) VCC = 3.3V TA = 25°C NRZ PRBS-7 EQ = Off PE = Off 50 30 20 10 TA = 25°C 3.125 Gbps NRZ PRBS-7 VID = 350 mV PE = Off EQ = Off 40 30 20 10 0 0 0 0.8 1.6 2.4 3.2 4.0 0 DATA RATE (Gbps) 1.32 1.98 2.64 3.3 INPUT COMMON MODE VOLTAGE (V) Figure 14. Total Jitter as a Function of Data Rate Figure 15.
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DS25CP102 SNLS262E – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) 120 VCC = 3.3V TA = 25°C NRZ PRBS7 Dual Buffer SUPPLY CURRENT (mA) 110 100 PE = ON 90 PE = OFF 80 70 60 0 0.8 1.6 2.4 3.2 4.0 DATA RATE (Gbps) 12 Figure 18. Supply Current as a Function of Data Rate and PE Level Figure 19. A 3.125 Gbps NRZ PRBS-7 without PE or EQ After 2" Differential FR-4 Stripline H: 50 ps / DIV, V: 100 mV / DIV Figure 20. A 3.
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DS25CP102 www.ti.com SNLS262E – OCTOBER 2007 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision D (March 2013) to Revision E • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DS25CP102TSQ/NOPB WQFN RGH 16 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 DS25CP102TSQX/NOPB WQFN RGH 16 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS25CP102TSQ/NOPB WQFN RGH 16 1000 210.0 185.0 35.0 DS25CP102TSQX/NOPB WQFN RGH 16 4500 367.0 367.0 35.
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PACKAGE OUTLINE RGH0016A WQFN - 0.8 mm max height SCALE 3.500 WQFN 4.1 3.9 B A PIN 1 INDEX AREA 0.5 0.3 0.3 0.2 4.1 3.9 DETAIL OPTIONAL TERMINAL TYPICAL C 0.8 MAX SEATING PLANE (0.1) TYP 2.6 0.1 5 8 SEE TERMINAL DETAIL 12X 0.5 4 9 4X 1.5 1 12 16X PIN 1 ID (OPTIONAL) 13 16 16X 0.3 0.2 0.1 0.05 C A C B 0.5 0.3 4214978/A 10/2013 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2.
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EXAMPLE BOARD LAYOUT RGH0016A WQFN - 0.8 mm max height WQFN ( 2.6) SYMM 16 13 SEE DETAILS 16X (0.6) 16X (0.25) 1 12 (0.25) TYP SYMM (3.8) (1) 9 4 12X (0.5) 5X ( 0.2) VIA 8 5 (1) (3.8) LAND PATTERN EXAMPLE SCALE:15X 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND METAL SOLDER MASK OPENING METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4214978/A 10/2013 NOTES: (continued) 4.
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EXAMPLE STENCIL DESIGN RGH0016A WQFN - 0.8 mm max height WQFN SYMM (0.675) METAL TYP 13 16 16X (0.6) 16X (0.25) 12 1 (0.25) TYP (0.675) SYMM (3.8) 12X (0.5) 9 4 8 5 4X (1.15) (3.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 78% PRINTED SOLDER COVERAGE BY AREA SCALE:15X 4214978/A 10/2013 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.
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